AD1819BJSTZ Analog Devices Inc, AD1819BJSTZ Datasheet - Page 18

• Manufacturer Part Number: AD1819BJSTZ
• Description: IC CODEC AUDIO 16BIT 48LQFP
• Manufacturer: Analog Devices Inc
• Type: Audio Codec '97r

Specifications of AD1819BJSTZ

• Data Interface: Serial
• Resolution (bits): 16 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• S/n Ratio, Adcs / Dacs (db) Typ: 90 / 90
• Dynamic Range, Adcs / Dacs (db) Typ: 87 / 90
• Voltage - Supply, Analog: 4.5 V ~ 5.5 V
• Voltage - Supply, Digital: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Single Supply Voltage (typ): 5V
• Single Supply Voltage (min): 4.5V
• Single Supply Voltage (max): 5.5V
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD1819B
Sample Rate 0 (Index 78h)
SR0 [15:0]
Sample Rate 1 (Index 7Ah)
SR1 [15:0]
Vendor ID (Index 7Ch–7Eh)
S [7:0]
F [7:0]
T [7:0]
REV [7:0]
DIGITAL INTERFACE
AD1819B AC-Link Digital Serial Interface Protocol
The AD1819B incorporates an AC'97 5-pin digital serial interface that links it to a digital controller. AC-Link is a bidirectional, fixed
rate, serial PCM digital stream. It handles multiple input, and output audio streams, as well as control register accesses employing a
time division multiplexed (TDM) scheme. The AC-Link architecture divides each audio frame into 12 outgoing and 12 incoming
data streams, up to 20-bit sample resolution. The AD1819B uses 16-bit samples. The data streams include:
AC ’97 Protocol
• TAG
• Control
• Status
• PCM Playback
• PCM Record Data
Synchronization of all AC-Link data transactions is signaled by the AC’97 controller. The AD1819B drives the serial bit clock onto
AC-Link, which the AC’97 controller then qualifies with a synchronization signal to construct audio frames.
SYNC, which is fixed at 48 kHz, is derived by dividing down the serial bit clock (BIT_CLK) by 256. The BIT_CLK is fixed at
12.288 MHz. AC-Link serial data is updated on each rising edge of BIT_CLK. The receiver of AC-Link data, the AD1819B for outgo-
ing data and the AC’97 controller for incoming data, samples each serial bit on the falling edge of BIT_CLK. SYNC must remain
high for a minimum of 1 BIT_CLK up to a maximum duration of 16 BIT_CLKs at the beginning of each audio frame. The first 16
bits of the audio frame is defined as the “Tag Phase.” The remainder of the audio frame is the “Data Phase.” The AD1819B uses
SYNC to define the beginning of the audio frame.
R
N
7
R
N
7
R
N
7
R
N
7
Control Register Write Port
Control Register Read Port
2-Channel Composite PCM Output Stream
2-Channel Composite PCM Input Stream
8
A
C
E
e
u
e
u
e
u
e
u
h
h
g
g
h
g
h
g
m
m
m
m
N
S
N
S
N
V
N
V
a
a
n e
n e
a
a
a
a
m
m
m
m
m
m
d
d
p
p
e
e
e
o
e
o
e l
e l
I r
I r
R
R
D
D
a
a
e t
e t
1
2
0
1
Writing to this register allows the user to program the sampling frequency from 7 kHz (1B58h) to 48 kHz (BB80h)
in 1 Hz increments. Programming a value greater than 48 kHz or less than 7 kHz may cause unpredictable results.
Writing to this register allows the user to program the sampling frequency from 7 kHz (1B58h) to 48 kHz (BB80h)
in 1 Hz increments. The sample rate may be multiplied by 8/7 or 10/7 by setting Bits D6 and D5 in Register 76h.
This register is ASCII encoded to “A.”
This register is ASCII encoded to “D.”
This register is ASCII encoded to “S.”
Revision Register field contains the revision number.
These bits are read-only and should be verified before accessing vendor-defined features.
S
S
D
D
D
D
R
R
T
F
0
1
5 1
5 1
5 1
5 1
7
7
1
1
5
5
S
S
D
R
D
R
D
D
F
T
0
1
4 1
4 1
4 1
4 1
6
6
1
1
4
4
S
S
D
D
D
D
R
R
T
F
0
1
3 1
3 1
3 1
3 1
5
5
1
1
3
3
S
S
D
D
D
D
R
R
F
T
2 1
0
2 1
1
2 1
2 1
4
4
1
1
2
2
S
S
D
R
D
R
D
D
F
T
0
1
1 1
1 1
1 1
1 1
3
3
1
1
1
1
1 Input and Output
2 Output Slots
2 Input Slots
2 Output Slots
2 Input Slots
S
S
D
D
D
D
R
R
T
F
0
1
0 1
0 1
0 1
0 1
2
2
1
1
0
0
S
S
D
D
D
D
R
R
F
T
–18–
0
1
1
1
9
9
9
9
9
9
S
S
D
D
D
D
T
R
R
F
0
8
0
8
1
8
8
0
8
8
R
S
S
D
D
D
D
R
R
S
E
0
1
7
V
7
7
7
7
7
7
7
R
S
S
D
D
D
D
R
R
E
S
6
0
1
V
6
6
6
6
6
6
6
R
S
S
D
D
D
D
R
R
S
E
5
V
5
0
5
1
5
5
5
5
5
R
S
S
D
R
D
R
D
D
E
S
4
0
1
V
4
4
4
4
4
4
4
R
S
S
D
D
D
D
R
R
S
E
3
0
1
V
3
3
3
3
3
3
3
R
S
S
D
D
D
D
R
R
S
E
2
V
2
0
2
1
2
2
2
2
2
R
S
S
D
D
D
D
R
R
E
S
1
0
1
V
1
1
1
1
1
1
1
R
S
S
D
D
D
D
R
R
S
E
0
V
0
1
0
0
0
0
0
0
0
D
B
D
B
D
4
D
5
1
3
B
B
e
e
e
e
4
0
a f
8
a f
8
a f
a f
REV. 0
4
3
0
0
h
h
u
u
u
u
h
h
t l
t l
t l
t l