AD1819BJSTZ Analog Devices Inc, AD1819BJSTZ Datasheet - Page 6

IC CODEC AUDIO 16BIT 48LQFP

AD1819BJSTZ

Manufacturer Part Number
AD1819BJSTZ
Description
IC CODEC AUDIO 16BIT 48LQFP
Manufacturer
Analog Devices Inc
Type
Audio Codec '97r
Datasheet

Specifications of AD1819BJSTZ

Data Interface
Serial
Resolution (bits)
16 b
Number Of Adcs / Dacs
2 / 2
Sigma Delta
Yes
S/n Ratio, Adcs / Dacs (db) Typ
90 / 90
Dynamic Range, Adcs / Dacs (db) Typ
87 / 90
Voltage - Supply, Analog
4.5 V ~ 5.5 V
Voltage - Supply, Digital
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
48-LQFP
Single Supply Voltage (typ)
5V
Single Supply Voltage (min)
4.5V
Single Supply Voltage (max)
5.5V
Package Type
LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AD1819BJSTZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Part Number:
AD1819BJSTZ-REEL
Manufacturer:
BUSSMANN
Quantity:
1 000
AD1819B
TIMING PARAMETERS (GUARANTEED OVER OPERATING TEMPERATURE RANGE)
Parameter
RESET Active Low Pulsewidth
RESET Inactive to BIT_CLK Start-Up Delay
SYNC Active High Pulsewidth
SYNC Low Pulsewidth
SYNC Inactive to BIT_CLK Start-Up Delay
BIT_CLK Frequency
BIT_CLK Period
BIT_CLK Output Jitter*
BIT_CLK High Pulsewidth
BIT_CLK Low Pulsewidth
SYNC Frequency
SYNC Period
Setup to Falling Edge of BIT_CLK
Hold from Falling Edge of BIT_CLK
BIT_CLK Rise Time
BIT_CLK Fall Time
SYNC Rise Time
SYNC Fall Time
SDATA_IN Rise Time
SDATA_IN Fall Time
SDATA_OUT Rise Time
SDATA_OUT Fall Time
End of Slot 2 to BIT_CLK, SDATA_IN Low
Setup to Trailing Edge of RESET (Applies to
Rising Edge of RESET to HI-Z Delay
*Output Jitter is directly dependent on crystal input jitter.
SYNC, SDATA_OUT)
BIT_CLK
BIT_CLK
SYNC
RESET
BIT_CLK
SYNC
Figure 3. Clock Timing
Figure 2. Warm Reset
Figure 1. Cold Reset
t
SYNC_HIGH
t
RST_LOW
t
CLK_HIGH
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
RST_LOW
RST2CLK
SYNC_HIGH
SYNC_LOW
SYNC2CLK
CLK_PERIOD
CLK_HIGH
CLK_LOW
SYNC_PERIOD
SETUP
HOLD
RISE CLK
FALL CLK
RISE SYNC
FALL SYNC
RISE DIN
FALL DIN
RISE DOUT
FALL DOUT
S2_PDOWN
SETUP2RST
OFF
t
CLK_PERIOD
–6–
t
t
SYNC_PERIOD
SYNC_HIGH
t
CLK_LOW
t
t
RST2CLK
SYNC_LOW
t
RST2CLK
Min
1.0
162.8
0.0814
162.8
32.56
32.56
15.0
15.0
15
Typ
1.3
19.5
12.288
81.4
40.7
40.7
48.0
20.8
4
4
4
4
4
4
4
4
Max
750
48.84
48.84
1.0
25
Units
ns
ns
MHz
ns
ps
ns
ns
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
REV. 0
s
s
s
s
s

Related parts for AD1819BJSTZ