AD1819BJSTZ Analog Devices Inc, AD1819BJSTZ Datasheet - Page 20

• Manufacturer Part Number: AD1819BJSTZ
• Description: IC CODEC AUDIO 16BIT 48LQFP
• Manufacturer: Analog Devices Inc
• Type: Audio Codec '97r

Specifications of AD1819BJSTZ

• Data Interface: Serial
• Resolution (bits): 16 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• S/n Ratio, Adcs / Dacs (db) Typ: 90 / 90
• Dynamic Range, Adcs / Dacs (db) Typ: 87 / 90
• Voltage - Supply, Analog: 4.5 V ~ 5.5 V
• Voltage - Supply, Digital: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Single Supply Voltage (typ): 5V
• Single Supply Voltage (min): 4.5V
• Single Supply Voltage (max): 5.5V
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD1819B
SDATA_OUT’s composite stream is MSB justified (MSB first) with all nonvalid slots’ bit positions stuffed with 0s by the
AC’97 controller. The AD1819B ignores invalid slots.
In the event that there are less than 20 valid bits within an assigned and valid time slot, the AC’97 controller always stuffs all trailing
nonvalid bit positions of the 20-bit slot with 0s. The AD1819B ignores unused bits.
As an example, consider an 8-bit sample stream being played out to one of the AD1819B’s DACs. The first 8-bit positions are pre-
sented to the DAC (MSB justified), followed by the next 12 bit positions, which are stuffed with 0s by the AC’97 controller.
When mono audio sample streams are output from the AC’97 controller, it is necessary that BOTH left and right stream time slots
be filled with the same data.
Slot 1: Command Address Port
The command port is used to control features and request status (see Audio Input Frame Slots l and 2) for AD1819B functions
including, but not limited to, mixer settings and power management (refer to the control register section of this specification).
The control interface architecture supports up to sixty-four 16-bit read/write registers, addressable on even byte boundaries. Only the
even registers (00h, 02h, etc.) are valid, odd register (01h, 03h, etc.) accesses are discouraged (defaulting to the preceding even byte
boundary—i.e., a read to 01h will return the 16-bit contents of 00h). Note that shadowing of the control register file on the AC’97
controller is an option left open to the implementation of the AC’97 controller. The AD1819B’s control register file is readable as
well as writable.
Audio output frame Slot 1 communicates control register address, and write/read command information to AD1819B.
Command Address Port Bit Assignments:
Bit (19)
Bit (18:12)
Bit (11:0)
The first bit (MSB) sampled by the AD1819B indicates whether the current control transaction is a read or a write operation. The
following 7-bit positions communicate the targeted control register address. The trailing 12-bit positions within the slot are reserved.
Slot 2: Command Data Port
The command data port is used to deliver 16-bit control register write data in the event that the current command port operation is a
write cycle (as indicated by Slot 1, Bit 19).
Bit (19:4)
Bit (3:0)
If the current command port operation is not a write, the entire slot time should be stuffed with 0s by the AC’97 controller.
Slot 3: PCM Playback Left Channel
Audio output frame Slot 3 is the composite digital audio left playback stream. In a typical “Games Compatible” PC this slot is com-
posed of standard PCM (.wav) output samples digitally mixed (on the AC’97 controller or host processor) with music synthesis
output samples. If a sample stream of resolution less than 20 bits is transferred, the AC’97 controller should stuff all trailing
nonvalid bit positions within this time slot with 0s.
Slot 4: PCM Playback Right Channel
Audio output frame Slot 4 is the composite digital audio right playback stream. In a typical “Games Compatible” PC this slot is
composed of standard PCM (.wav) output samples digitally mixed (on the AC’97 controller or host processor) with music synthesis
output samples. If a sample stream of resolution less than 20 bits is transferred, the AC’97 controller should stuff all trailing nonvalid bit
positions within this time slot with 0s.
Read/Write Command
Control Register Index
Reserved
Control Register Write Data
Reserved
SDATA_OUT
BIT_CLK
Figure 11. Start of an Audio Output Frame
SYNC
END OF PREVIOUS
AUDIO FRAME
AD1819A SAMPLES SYNC ASSERTION HERE
(1 = Read, 0 = Write)
(64 16-Bit Locations, Addressed On Even Byte Boundaries)
(Stuffed with 0s)
(Stuffed with 0s If Current Operation Is Not a Write)
(Stuffed with 0s)
AC’97 CONTROLLER SAMPLES
FIRST SDATA_OUT BIT OF FRAME HERE
–20–
FRAME
VALID
SLOT (1) SLOT (2)
REV. 0