UDA1380TT/N2,518 NXP Semiconductors, UDA1380TT/N2,518 Datasheet - Page 44

• Manufacturer Part Number: UDA1380TT/N2,518
• Description: IC AUDIO CODER-DECODER 32-TSSOP
• Manufacturer: NXP Semiconductors
• Type: Stereo Audior

Specifications of UDA1380TT/N2,518

• Data Interface: I²C, Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: No
• S/n Ratio, Adcs / Dacs (db) Typ: 97 / 100
• Voltage - Supply, Analog: 2.4 V ~ 3.6 V
• Voltage - Supply, Digital: 2.4 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935270659518; UDA1380TT-T; UDA1380TT-T

NXP Semiconductors
Table 53 ADC volume control setting bits
11.12 PGA settings and mute
Table 54 Register address 21H
Table 55 Description of register bits
2004 Apr 22
Symbol
Default
Symbol
Default
MR_DEC7
ML_DEC7
14 to 12
Stereo audio coder-decoder
for MD, CD and MP3
BIT
BIT
BIT
15
0
0
0
0
0
0
1
1
1
1
1
1
:
:
MT_ADC
−
MR_DEC6
ML_DEC6
MT_ADC
SYMBOL
15
1
7
−
0
0
0
0
0
0
0
1
0
0
0
0
0
:
:
MR_DEC5
ML_DEC5
14
−
0
6
−
0
1
1
1
0
0
0
1
0
0
0
0
0
:
:
Decimator mute. A 1-bit value to enable the digital linear mute. When this bit is
logic 0: no muting. When this bit is logic 1: muting. Default value 1.
default value 000
13
MR_DEC4
ML_DEC4
−
0
−
0
5
1
0
0
0
0
0
1
0
0
0
0
0
:
:
12
−
0
4
−
0
MR_DEC3
ML_DEC3
0
1
1
0
0
0
1
0
0
0
0
0
:
:
44
PGA_GAIN
PGA_GAIN
CTRLR3
CTRLL3
11
0
3
0
MR_DEC2
ML_DEC2
DESCRIPTION
0
1
1
0
0
0
1
1
0
0
0
0
:
:
PGA_GAIN
PGA_GAIN
CTRLR2
CTRLL2
MR_DEC1
10
ML_DEC1
0
2
0
0
1
1
1
0
0
1
0
1
1
0
0
:
:
PGA_GAIN
PGA_GAIN
CTRLR1
CTRLL1
MR_DEC0
ML_DEC0
9
0
1
0
0
1
0
0
1
0
1
0
1
0
1
0
:
:
Product specification
UDA1380
PGA_GAIN
PGA_GAIN
GAIN (dB)
0 (default)
CTRLR0
CTRLL0
−62.5
−63.5
23.5
−0.5
−62
−63
0.5
−∞
24
23
8
0
0
0
1
:
: