CY7C68300C-56PVXC Cypress Semiconductor Corp, CY7C68300C-56PVXC Datasheet - Page 13

• Manufacturer Part Number: CY7C68300C-56PVXC
• Description: IC USB 2.0 BRIDGE AT2LP 56-SSOP
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr
• Type: USB to ATA/ATAPI Bridger

Specifications of CY7C68300C-56PVXC

• Package / Case: 56-SSOP
• Controller Type: USB 2.0 Controller
• Interface: I²C
• Voltage - Supply: 3.15 V ~ 3.45 V
• Current - Supply: 50mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Bits: 48
• Operating Temperature Range: 0 C to + 70 C
• Supply Current: 10 mA
• Operating Supply Voltage: 3.3 V
• Controller Family/series: (8051) USB
• Core Size: 8 Bit
• No. Of I/o's: 6
• Embedded Interface Type: I2C, USB
• Digital Ic Case Style: SSOP
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Package Type: SSOP
• Rad Hardened: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY4615B - KIT USB TO ATA REFERENCE DESIGN
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-2266-5; CY7C68300C-56PVXC

Table 1. AT2LP Pin Descriptions (continued)
Note Italic pin names denote pin functionality during CY7C68300A compatibility mode
Additional Pin Descriptions
The following sections provide additional pin information.
DPLUS, DMINUS
DPLUS and DMINUS are the USB signaling pins; they must be
tied to the D+ and D– pins of the USB connector. Because they
operate at high frequencies, the USB signals require special
consideration when designing the layout of the PCB. See
General PCB Layout Recommendations for USB Mass Storage
Designs
When RESET# is released, the assertion of the internal pull up
on D+ is gated by a combination of the state of the
VBUS_ATA_ENABLE pin, the value of configuration address
0x08 bit 0 (DRVPWRVLD Enable), and the detection of a
non-removable ATA/ATAPI drive on the IDE bus. See
a description of this relationship.
Table 2. D+ Pull Up Assertion Dependencies
SCL, SDA
The clock and data pins for the I
the configuration EEPROM and to 2.2K pull up resistors tied to
V
must still be connected to pull up resistors. The SCL and SDA
pins are active for several milliseconds at startup.
Document 001-05809 Rev. *E
TQFP
CC
100
ATA/ATAPI Drive Detected
100
99
DRVPWRVLD Enable Bit
. If no EEPROM is used in the design, the SCL and SDA pins
[3]
State of D+ pull up
on page 40 for PCB layout recommendations.
QFN
54
56
53
VBUS_ATA_EN
[3]
SSOP
56
4
5
Yes
1
1
1
Pin Name
ATAPUEN
2
C port must be connected to
GND
(NC)
No
1
1
1
Yes
1
0
1
No
1
0
0
Type
GND
Pin
I/O
Yes
0
1
0
Table 2
No
Default State
0
1
0
at Startup
for
XTALIN, XTALOUT
The AT2LP requires a 24 MHz (
internal timing. Typically, a 24 MHz (12 pF, 500 μW,
parallel-resonant, fundamental mode) crystal is used, but a
24 MHz square wave (3.3V, 50/50 duty cycle) from another
source can also be used. If a crystal is used, connect its pins to
XTALIN and XTALOUT, and also through 12 pF capacitors to
GND as shown in
apply it to XTALIN and leave XTALOUT unconnected.
Figure 7. XTALIN/XTALOUT Diagram
Ground.
Bus powered ATA pull up voltage source (see
on page 15).
Alternate function: General purpose input when the
EEPROM configuration byte 8 has bit 7 set to ‘1’. The input
value is reported through EP1IN (byte 0, bit 2).
12pF
XTALIN
CY7C68300C, CY7C68301C
CY7C68320C, CY7C68321C
Figure
Pin Description
7. If an alternate clock source is used,
24MHz Xtal
±
100 ppm) signal to derive
XTALOUT
Page 13 of 42
ATAPUEN
12pF
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