CY7C68300C-56PVXC Cypress Semiconductor Corp, CY7C68300C-56PVXC Datasheet - Page 19
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CY7C68300C-56PVXC
Manufacturer Part Number
CY7C68300C-56PVXC
Description
IC USB 2.0 BRIDGE AT2LP 56-SSOP
Manufacturer
Cypress Semiconductor Corp
Series
CY7Cr
Type
USB to ATA/ATAPI Bridger
Datasheets
1.CY7C68300C-56PVXC.pdf
(42 pages)
2.CY7C68320C-100AXA.pdf
(44 pages)
3.CY7C68300C-56PVXC.pdf
(42 pages)
Specifications of CY7C68300C-56PVXC
Package / Case
56-SSOP
Controller Type
USB 2.0 Controller
Interface
I²C
Voltage - Supply
3.15 V ~ 3.45 V
Current - Supply
50mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Number Of Bits
48
Operating Temperature Range
0 C to + 70 C
Supply Current
10 mA
Operating Supply Voltage
3.3 V
Controller Family/series
(8051) USB
Core Size
8 Bit
No. Of I/o's
6
Embedded Interface Type
I2C, USB
Digital Ic Case Style
SSOP
Supply Voltage Range
3V To 3.6V
Rohs Compliant
Yes
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Operating Temperature (max)
70C
Package Type
SSOP
Rad Hardened
No
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
CY4615B - KIT USB TO ATA REFERENCE DESIGN
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
428-2266-5
CY7C68300C-56PVXC
CY7C68300C-56PVXC
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY7C68300C-56PVXC
Manufacturer:
HITACHI
Quantity:
2 000
Company:
Part Number:
CY7C68300C-56PVXC
Manufacturer:
CY
Quantity:
8
Part Number:
CY7C68300C-56PVXC
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
Fused Memory Data
When no EEPROM is detected at startup, the AT2LP
enumerates with the VID/PID/DID values that are stored in the
fused memory space. These values can be programmed into the
AT2LP during chip manufacturing for high volume applications to
avoid the need for an external EEPROM in some designs.
Contact your local Cypress Semiconductor sales office for more
information on this feature.
If no factory programming has been done, the values returned
from the fused memory space would all be 0x00, which is not a
valid mode of operation. In this case the chip uses the manufac-
turing mode and return the default descriptors (VID/PID of
0x4B4/0x6830). An EEPROM must be used with designs that do
not use factory-programmed chips in order to identify the device
as your company’s product.
Normal Mass Storage Mode
In Normal Mass Storage Mode, the chip behaves as a USB 2.0
to ATA/ATAPI bridge. This includes all typical USB device states
(powered, configured, etc.). The USB descriptors are returned
according to the values stored in the external EEPROM or fused
memory space. A unique serial number is required for Mass
Storage Class Bulk-Only Transport compliance, which is one
reason why an EEPROM or factory-programmed part is needed.
Board Manufacturing Test Mode
In Board Manufacturing Test Mode the AT2LP behaves as a USB
2.0 device but the ATA/ATAPI interface is not fully active. This
mode must not be used for mass storage operation in a finished
design. In this mode, the AT2LP enable reading from and writing
to the EEPROM, and for board level testing, through vendor
specific ATAPI commands utilizing the CBW Command Block as
described in the USB Mass Storage Class Bulk-Only Transport
Specification. There is a vendor-specific ATAPI command for
Table 7. Command Block Wrapper
Document 001-05809 Rev. *B
0–3
4–7
8–11 (08h–0Bh)
12 (0Ch)
13 (0Dh)
14 (0Eh)
15–30 (0Fh1Eh)
Offset
Dir
7
Reserved (0)
Obsolete
6
Reserved (0)
5
CBWCB (CfgCB or MfgCB)
dCBWDataTransferLength
DCBWSignature
bwCBWFLAGS
4
dCBWTag
EEPROM accesses (CfgCB) and one for board level testing
(MfgCB), as described in the following sections.
There is a convenient method available for starting the AT2LP in
Board Manufacturing Test Mode to enable reprogramming of
EEPROMs without a mass storage device attached. If the ATA
Reset (ARESET#) line is LOW on power up, the AT2LP enters
Board Manufacturing Test Mode. It is recommended that a 10k
resistor be used to pull ARESET# to LOW. An easy way to pull
the ARESET# line LOW is to short pins 1 and 3 on the 40-pin
ATA connector with a 10k resistor, that ties the ARESET# line to
the required pull down on DD7.
CfgCB
The cfg_load and cfg_read vendor-specific commands are
passed down through the bulk pipe in the CBWCB portion of the
CBW. The format of this CfgCB is shown as follows. Byte 0 is a
vendor-specific command designator whose value is config-
urable and set in the configuration data (address 0x04). Byte 1
must be set to 0x26 to identify it as a CfgCB command. Byte2 is
reserved and must be set to zero. Byte 3 is used to determine
the memory source to write/read. For the AT2LP, this byte must
be set to 0x02, indicating the EEPROM is present. Bytes 4 and
5 are used to determine the start address, which must always be
0x0000. Bytes 6 through 15 are reserved and must be set to
zero.
The data transferred to the EEPROM must be in the format
specified in
size is 255 bytes.
The data transfer length is determined by the CBW Data Transfer
Length specified in bytes 8 through 11 (dCBWDataTransfer-
Length) of the CBW (refer to
command is determined by the direction bit specified in byte 12,
bit 7 (bmCBWFlags) of the CBW (refer to
Bits
3
Reserved (0)
Table 11
bCBWCBLength
CY7C68300C, CY7C68301C
CY7C68320C, CY7C68321C
of this data sheet. Maximum data transfer
2
bCBWLUN
Table
7). The type/direction of the
1
Table
7).
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