CY7C68300C-56PVXC Cypress Semiconductor Corp, CY7C68300C-56PVXC Datasheet - Page 3

• Manufacturer Part Number: CY7C68300C-56PVXC
• Description: IC USB 2.0 BRIDGE AT2LP 56-SSOP
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr
• Type: USB to ATA/ATAPI Bridger

Specifications of CY7C68300C-56PVXC

• Package / Case: 56-SSOP
• Controller Type: USB 2.0 Controller
• Interface: I²C
• Voltage - Supply: 3.15 V ~ 3.45 V
• Current - Supply: 50mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Bits: 48
• Operating Temperature Range: 0 C to + 70 C
• Supply Current: 10 mA
• Operating Supply Voltage: 3.3 V
• Controller Family/series: (8051) USB
• Core Size: 8 Bit
• No. Of I/o's: 6
• Embedded Interface Type: I2C, USB
• Digital Ic Case Style: SSOP
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Package Type: SSOP
• Rad Hardened: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY4615B - KIT USB TO ATA REFERENCE DESIGN
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-2266-5; CY7C68300C-56PVXC

The ATA/ATAPI port of the AT2LP is connected to one or two
mass storage devices. A 4 KB buffer maximizes ATA/ATAPI data
transfer rates by minimizing losses due to device seek times. The
ATA interface supports ATA PIO modes 0, 3, and 4, multiword
DMA mode 2, and Ultra DMA modes 2, 3, and 4.
The device initialization process is configurable, enabling the
AT2LP to initialize ATA/ATAPI devices without software inter-
vention.
CY7C68300A Compatibility
As mentioned in the previous section, the CY7C68300C/301C
contains a backward compatibility mode that enables it to be
used in existing EZ-USB AT2 (CY7C68300A) designs. The
backward compatibility mode is enabled by programming the
EEPROM with the CY7C68300A signature.
During startup, the AT2LP checks the I
with a valid signature in the first two bytes. If the signature is
0x4D4D, the AT2LP configures itself for pin-to-pin compatibility
with the AT2 and begins normal mass storage operation. If the
signature is 0x534B, the AT2LP configures itself with the AT2LP
pinout and begins normal mass storage operation.
Refer to the logic flow in
pinout selection process.
Most designs that use the AT2 can migrate to the AT2LP with no
changes to either the board layout or EEPROM data. Cypress
has published an application note focused on migrating from the
AT2 to the AT2LP to help expedite the process. It can be
downloaded from the Cypress website (http://www.cypress.com)
or obtained through a Cypress representative.
Document 001-05809 Rev. *B
Figure 1
for more information on the
2
C™ bus for an EEPROM
Figure 1. Simplified Pinout Selection Flowchart
Normal Operation
Read EEPROM
(CY7C68300A)
EZ-USB AT2
EEPROM
Signature
0x4D4D?
Pinout
CY7C68300C, CY7C68301C
CY7C68320C, CY7C68321C
Yes
Set
No
EZ-USB AT2LP
(CY7C68300B)
Pinout
Set
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