LAN9500-ABZJ SMSC, LAN9500-ABZJ Datasheet - Page 61

• Manufacturer Part Number: LAN9500-ABZJ
• Description: IC USB 2.0 ETHER CTRLR 56-QFN
• Manufacturer: SMSC
• Type: Single Chip MAC and PHY Controllerr

Specifications of LAN9500-ABZJ

• Controller Type: USB 2.0 Controller
• Interface: MII
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 78mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-QFN
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: IEEE 802.3 or IEEE 802.3u
• Data Rate: 10 Mbps or 100 Mbps
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 0 V
• Supply Current (max): 97.5 mA, 135.2 mA
• Maximum Operating Temperature: + 70 C
• Ethernet Connection Type: 10BASE-T or 100BASE-TX
• Maximum Power Dissipation: 0.6657 W (Typ)
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1071

USB 2.0 to 10/100 Ethernet Controller
Datasheet
SMSC LAN950x Family
8.6
Crystal Cut
Crystal Oscillation Mode
Crystal Calibration Mode
Frequency
Frequency Tolerance @ 25
Frequency Stability Over Temp
Frequency Deviation Over Time
Total Allowable PPM Budget
Shunt Capacitance
Load Capacitance
Drive Level
Equivalent Series Resistance
Operating Temperature Range
XI Pin Capacitance
XO Pin Capacitance
PARAMETER
Clock Circuit
The device can accept either a 25MHz crystal (preferred) or a 25MHz single-ended clock oscillator (+/-
50ppm) input. If the single-ended clock oscillator method is implemented, XO should be left
unconnected and XI should be driven with a nominal 0-3.3V clock signal. The input clock duty cycle
is 40% minimum, 50% typical and 60% maximum.
It is recommended that a crystal utilizing matching parallel load capacitors be used for the crystal
input/output signals (XI/XO). See
Note 8.18 The maximum allowable values for Frequency Tolerance and Frequency Stability are
Note 8.19 Frequency Deviation Over Time is also referred to as Aging.
Note 8.20 The total deviation for the Transmitter Clock Frequency is specified by IEEE 802.3u as
Note 8.21 0
Note 8.22 +70
Note 8.23 This number includes the pad, the bond wire and the lead frame. PCB capacitance is not
application dependant. Since any particular application must meet the IEEE +/-50 PPM
Total PPM Budget, the combination of these two values must be approximately +/-45 PPM
(allowing for aging).
+/- 50 PPM.
included in this value. The XO/XI pin and PCB capacitance values are required to
accurately calculate the value of the two external load capacitors. These two external load
capacitors determine the accuracy of the 25.000 MHz frequency.
o
C for commercial version, -40
o
C
o
C for commercial version, +85
SYMBOL
F
F
F
Table 8.22 Crystal Specifications
F
P
C
temp
C
R
fund
age
tol
W
O
L
1
Table 8.22
DATASHEET
Note 8.21
MIN
300
Parallel Resonant Mode
-
-
-
-
-
-
-
-
-
-
61
o
Fundamental Mode
for the recommended crystal specifications.
C for industrial version.
o
C for industrial version.
AT, typ
+/-3 to 5
25.000
20 typ
NOM
7 typ
3 typ
3 typ
-
-
-
-
-
-
Note 8.22
+/-50
+/-50
+/-50
MAX
50
-
-
-
-
-
-
-
UNITS
PPM
PPM
PPM
PPM
Ohm
MHz
uW
Revision 1.0 (05-17-10)
pF
pF
o
pF
pF
C
Note 8.18
Note 8.18
Note 8.19
Note 8.20
Note 8.23
Note 8.23
NOTES