LAN9512-JZX SMSC, LAN9512-JZX Datasheet - Page 31

IC USB 2.0 ETHER CTRLR 64QFN

LAN9512-JZX

Manufacturer Part Number
LAN9512-JZX
Description
IC USB 2.0 ETHER CTRLR 64QFN
Manufacturer
SMSC
Datasheets

Specifications of LAN9512-JZX

Controller Type
Ethernet Controller
Interface
IEEE 802.3
Voltage - Supply
3 V ~ 3.6 V
Current - Supply
231mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
64-QFN
Product
Ethernet Controllers
Standard Supported
802.3, 802.3u
Data Rate
1.5 Mbps to 480 Mbps
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3 V
Supply Current (max)
231 mA
Maximum Operating Temperature
+ 70 C
Ethernet Connection Type
10/100 Base-T
Maximum Power Dissipation
763 mW
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
For Use With
638-1093 - EVALUATION BOARD FOR LAN9512
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
638-1086

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
LAN9512-JZX
Manufacturer:
SMSC
Quantity:
5 510
Part Number:
LAN9512-JZX
Manufacturer:
SMSC
Quantity:
1 000
Part Number:
LAN9512-JZX
Manufacturer:
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Quantity:
20 000
Part Number:
LAN9512-JZX
0
USB 2.0 Hub and 10/100 Ethernet Controller
Datasheet
SMSC LAN9512/LAN9512i
BITS
BITS
1:0
7:2
3:2
1
0
Upstream USB Electrical Signaling Drive Strength Boost Bit for
Downstream Port 2 (BOOST_IOUT_2)
00 = Normal electrical drive strength
01 = Elevated electrical drive strength (+4% boost)
10 = Elevated electrical drive strength (+8% boost)
11 = Elevated electrical drive strength (+12% boost)
RESERVED
RESERVED
Reset (RESET)
Resets the internal memory back to nRESET assertion default settings.
0 = Normal Run/Idle State
1 = Force a reset of the registers to their default state
Note:
USB Attach and Write Protect (USB_ATTACH)
0 = Device is in configuration state
1 = Hub will signal a USB attach event to an upstream device, and the
internal memory (address range 00h - FEh) is “write-protected” to prevent
unintentional data corruption.
Note:
Table 3.8 Boost_3:2 Register (BOOST32) Format (continued)
During this reset, this bit is automatically cleared to its default value
of 0.
This bit is write once and is only cleared by assertion of the external
nRESET or POR.
Table 3.9 Status/Command Register (STCD) Format
DESCRIPTION
DESCRIPTION
DATASHEET
31
Revision 1.0 (11-24-09)
DEFAULT
DEFAULT
000000b
00b
00b
0b
1b

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