TDA8026ET/C2,551 NXP Semiconductors, TDA8026ET/C2,551 Datasheet - Page 20

• Manufacturer Part Number: TDA8026ET/C2,551
• Description: IC SMART CARD SLOT 64TFBGA
• Manufacturer: NXP Semiconductors

Specifications of TDA8026ET/C2,551

• Package / Case: 64-TFBGA
• Controller Type: Smart Card Interface
• Interface: I²C
• Voltage - Supply: 2.7 V ~ 5.5 V
• Current - Supply: 210mA
• Operating Temperature: -25°C ~ 85°C
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 25 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935288286551

NXP Semiconductors
TDA8026_1
Product data sheet
8.5.3.3 Bank 1 Register0 card slot 1 (address 01h) and card slot 2 (address 02h) write mode
bit descriptions
Table 12.
[1]
[2]
[3]
Bit
7
6
5 to 4
3
2
1
0
This bit cannot be written when the START bit is logic 1.
It is a mandatory condition for card slots 2 to 5 that only one card slot I/O line is enabled at a time. When
switching from one slot to another, the enabled I/O must be disabled before the I/O line for the required card
slot is enabled.
Remark: If both pins I/OUC1 and I/OUC2 are connected at the same time, this mandatory condition also
applies to card slot 1.
In synchronous mode, this bit cannot be written when START bit is logic 1.
Symbol
VCC1V8
I/OEN
REG[1:0]
PWDN
5V/3VN
WARM
START
Bank 1 Register0 card slot 1 (address 01h) and card slot 2 (address 02h) write
mode bit descriptions
[2]
[3]
All information provided in this document is subject to legal disclaimers.
[1]
[1]
Value Description
1
0
1
0
-
1
0
1
0
1
0
1
0
Rev. 1 — 9 March 2010
set to logic 1: a warm reset procedure is started
used together with the 5V/3VN bit
set to logic 1: pins I/OUCn are switched to pins I/O
set to logic 0: pins I/OUCn and I/O
internal pull-up resistor
See
slots 1 and card slots 2 bit allocation” on page 21
information
set to logic 1 to apply the CLKPD[1:0] bit clock settings to pin
CLK
set to logic 0 to apply the CLKDIV[1:0] bits clock options to pin
CLK
used together with VCC1V8 bit.
set to logic 0: by hardware when a START bit is detected or when
MUTE bit is set to logic 1
set to logic 1: starts the activation sequence and cold reset
procedure (only if the SUPL and PROT bits are logic 0 and the
PRES bit is logic 1)
set to logic 0: starts the deactivation sequence
set to logic 1: V
set to logic 0: V
set to logic 1 and the VCC1V8 bit is logic 0: V
set to logic 0 and the VCC1V8 bit is logic 0: V
(n)
(n)
Table 13 “Bank 1 CSb[7:0] Register0 (address 42h) card
for the selected card slot
for the selected card slot
CC(n)
CC(n)
= 1.8 V; ignores the 5V/3VN bit logic state
is set using the 5V/3VN bit
Multiple smart card slot interface IC
(n)
are high-impedance with
TDA8026
© NXP B.V. 2010. All rights reserved.
CC(n)
CC(n)
for detailed
(n)
= 5 V
= 3 V
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