DS21FF44 Maxim Integrated Products, DS21FF44 Datasheet - Page 42

• Manufacturer Part Number: DS21FF44
• Description: IC FRAMER E1 4X4 16CH 300-BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS21FF44

• Controller Type: E1 Framer
• Interface: Parallel/Serial
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 300mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 300-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

CCR6: COMMON CONTROL REGISTER 6 (Address = 1D Hex)
11.
There is a set of seven registers per framer that contain information on the current real time status of a
framer in the DS21Q44, Status Register 1 (SR1), Status Register 2 (SR2), Receive Information Register
(RIR), Synchronizer status Register (SSR) and a set of three registers for the onboard HDLC controller.
The specific details on the four registers pertaining to the HDLC controller are covered in Section 19 but
they operate the same as the other status registers in the DS21Q44 and this operation is described below.
When a particular event has occurred (or is occurring), the appropriate bit in one of these four registers
will be set to a one. All of the bits in SR1, SR2, and RIR1 registers operate in a latched fashion. The
Synchronizer status Register contents are not latched. This means that if an event or an alarm occurs and
a bit is set to a one in any of the registers, it will remain set until the user reads that bit. The bit will be
cleared when it is read and it will not be set again until the event has occurred again (or in the case of the
RSA1, RSA0, RDMA, RUA1, RRA, RCL, and RLOS alarms, the bit will remain set if the alarm is still
present).
The user will always precede a read of any of the SR1, SR2 and RIR registers with a write. The byte
written to the register will inform the framer which bits the user wishes to read and have cleared. The
user will write a byte to one of these registers, with a one in the bit positions he or she wishes to read and
a zero in the bit positions he or she does not wish to obtain the latest information on. When a one is
written to a bit location, the read register will be updated with the latest information. When a zero is
written to a bit position, the read register will not be updated and the previous value will be held. A write
(MSB)
TCLKSRC
SYMBOL
—
RESR
TESR
STATUS AND INFORMATION REGISTERS
—
—
—
—
—
—
POSITION
CCR6.7
CCR6.6
CCR6.5
CCR6.4
CCR6.3
CCR6.2
CCR6.1
CCR6.0
—
Not Assigned. Should be set to zero when written
Not Assigned. Should be set to zero when written
Not Assigned. Should be set to zero when written
Not Assigned. Should be set to zero when written
Not Assigned. Should be set to zero when written
Transmit Clock Source Select. This function allows the user
to internally select RCLK as the clock source for the transmit
side formatter.
0 = transmit side formatter clocked with signal applied at
TCLK pin. LOTC Mux function is operational (TCR1.7)
1 = transmit side formatter clocked with RCLK.
Receive Elastic Store Reset. Setting this bit from a zero to a
one will force the receive elastic store to a depth of one frame.
Receive data is lost during the reset. Should be toggled after
RSYSCLK has been applied and is stable. Do not leave this bit
set high.
Transmit Elastic Store Reset. Setting this bit from a zero to a
one will force the transmit elastic store to a depth of one frame.
Transmit data is lost during the reset. Should be toggled after
TSYSCLK has been applied and is stable. Do not leave this bit
set high.
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NAME AND DESCRIPTION
TCLKSRC
RESR
(LSB)
TESR