DS21FF44 Maxim Integrated Products, DS21FF44 Datasheet - Page 88

• Manufacturer Part Number: DS21FF44
• Description: IC FRAMER E1 4X4 16CH 300-BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS21FF44

• Controller Type: E1 Framer
• Interface: Parallel/Serial
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 300mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 300-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

SAMPLE/PRELOAD
A mandatory instruction for the IEEE 1149.1 specification. This instruction supports two functions. The
digital I/Os of the DS21Q44 can be sampled at the boundary scan register without interfering with the
normal operation of the device by using the Capture-DR state. SAMPLE/PRELOAD also allows the
DS21Q44 to shift data into the boundary scan register by JTDI using the Shift-DR state.
EXTEST
EXTEST allows testing of all interconnections to the DS21Q44. When the EXTEST instruction is
latched in the instruction register, the following actions occur. Once enabled by the Update-IR state, the
parallel outputs of all digital output pins will be driven. The boundary scan register will be connected
between JTDI and JTDO. The Capture-DR will sample all digital inputs into the boundary scan register.
BYPASS
When the BYPASS instruction is latched into the parallel instruction register, JTDI connects to JTDO
through the 1 bit bypass test register. This allows data to pass from JTDI to JTDO not affecting the
device’s normal operation.
IDCODE
When the IDCODE instruction is latched into the parallel instruction register, the Identification Test
register is selected. The device identification code will be loaded into the Identification register on the
rising edge of JTCLK following entry into the Capture-DR state. Shift-DR can be used to shift the
identification code out serially by JTDO. During Test-Logic-Reset, the identification code is forced into
the instruction register’s parallel output. The ID code will always have a ‘1’ in the LSB position. The
next 11 bits identify the manufacturer’s JEDEC number and number of continuation bytes followed by 16
bits for the device and 4 bits for the version. See Table 21-2. Table 21-3 lists the device ID codes for the
DS21Q42 and DS21Q44 devices.
Table 21-2. ID CODE STRUCTURE
Table 21-3. DEVICE ID CODES
HIGH-Z
All digital outputs of the DS21Q44 will be placed in a high impedance state. The BYPASS register will
be connected between JTDI and JTDO.
CLAMP
All digital outputs of the DS21Q44 will output data from the boundary scan parallel output while
connecting the bypass register between JTDI and JTDO. The outputs will not change during the CLAMP
instruction.
CONTENTS
LENGTH
DS21Q42
DS21Q44
DEVICE
MSB
(Contact Factory)
Version
4 bits
16-BIT NUMBER
0000h
0001h
(See Table 21-3)
Device ID
16 bits
88 of 117
“00010100001”
JEDEC
11 bits
1 bit
“1”
LSB