S-8233ACFE-TB Seiko Instruments, S-8233ACFE-TB Datasheet - Page 15

• Manufacturer Part Number: S-8233ACFE-TB
• Description: Battery Management 4.25V 3-Cell Serial
• Manufacturer: Seiko Instruments

Specifications of S-8233ACFE-TB

• Product: Charge Management
• Battery Type: Li-Ion Pack
• Output Voltage: 24 V
• Operating Supply Voltage: 2 V to 24 V
• Supply Current: 50 uA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: - 20 C
• Package / Case: SOP-14
• Mounting Style: SMD/SMT
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Rev.3.2
Over discharge condition
Delay circuits
CTL terminal
0 V battery charging function
If any one of the battery voltages falls below the over discharge detection voltage (V
under normal condition and it continues for the over discharge detection delay time (t
discharging FET turns off and discharging stops. This condition is called the over discharge condition.
When the discharging FET turns off, the VMP terminal voltage becomes equal to the VSS voltage and the
IC's current consumption falls below the power-down current consumption (I
the power-down condition. The VMP and VSS terminals are shorted by the R
discharge and power-down conditions.
The over charge detection delay time (t
over current detection delay time 1 (t
The delay times are calculated by the following equations:
If the CTL terminal is floated under normal condition, it is pulled up to the V
the charging and discharging FETs turn off to inhibit charging and discharging. Both charging and
discharging are also inhibited by applying the VCC terminal to the CTL terminal externally. At this time,
the VMP and VCC terminals are shorted by the R
This function is used to recharge the three serially-connected batteries after they self-discharge to 0 V.
When the 0 V charging start voltage (V
the charger, the charging FET gate is fixed to V
When the voltage between the gate sources of the charging FET becomes equal to or higher than the
turn-on voltage by the charger voltage, the charging FET turns on to start charging. At this time, the
discharging FET turns off and the charging current flows through the internal parasitic diode in the
discharging FET. If all the battery voltages become equal to or higher than the over discharge release
voltage (V
The power-down condition is canceled when the charger is connected and the voltage between VMP and
VSS is 3.0 V or higher (over current detection voltage 3). When all the battery voltages becomes equal to
or higher than the over discharge release voltage (V
changes to the normal condition.
Caution: The delay time for over current detection 2 and 3 is fixed by an internal IC circuit. The
When the CTL terminal becomes equal to V
back to their appropriate conditions for the battery voltages.
Caution Please note unexpected behavior might occur when electrical potential difference
Caution: In the products without 0 V battery charging function, the resistance between VCC and
t
t
t
CU
DD
IOV1
[s] =Delay factor ( 1.07, 2.13, 3.19)×C4 [uF]
[s] =Delay factor ( 0.20, 0.40, 0.60)×C5 [uF]
_10
[s]=Delay factor ( 0.10, 0.20, 0.30)×C6 [uF]
VMP and between VSS and VMP are lower than the products with 0 V battery charging
function. It causes to that over charge detection voltage increases by the drop voltage of
R5 (see Figure 9 for a connection example) with sink current at VMP.
The COP output is undefined below 2.0 V on VCC-VSS voltage in the products without 0 V
battery charging function.
DU
delay time cannot be changed via an external capacitor.
between the CTL pin ('L' level) and VSS is generated through the external filter
(R
), the normal condition returns.
VSS
and C
Min. Typ.
VSS
) as a result of input voltage fluctuations.
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK
Max.
IOV1
Seiko Instruments Inc.
0CHAR
CU1
) are changed with external capacitors (C4 to C6).
to t
) or higher is applied to between VMP and VSS by connecting
SS
CU3
potential, charging and discharging are enabled and go
SS
), over discharge detection delay time (t
VCM
potential.
DU
resistor.
) in this condition, the over discharge condition
CC
PDN
VSM
potential in the IC, and both
). This condition is called
resistor under the over
DD
DD
S-8233A Series
) during discharging
) or longer, the
DD1
to t
DD3
), and
15