S-8233ACFE-TB Seiko Instruments, S-8233ACFE-TB Datasheet - Page 19

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S-8233ACFE-TB

Manufacturer Part Number
S-8233ACFE-TB
Description
Battery Management 4.25V 3-Cell Serial
Manufacturer
Seiko Instruments
Datasheets

Specifications of S-8233ACFE-TB

Product
Charge Management
Battery Type
Li-Ion Pack
Output Voltage
24 V
Operating Supply Voltage
2 V to 24 V
Supply Current
50 uA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
- 20 C
Package / Case
SOP-14
Mounting Style
SMD/SMT
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
S-8233ACFE-TB
Manufacturer:
SEIKO
Quantity:
51 000
Rev.3.2
Battery Protection IC Connection Example
[Description of Figure 9]
Battery 1
Battery 2
Battery 3
_10
R7 is the protection of the CTL when the CTL terminal voltage higher than V
300 Ω to 5 kΩ resister. If the CTL terminal voltage never greater than the V
connect to V
R11, R12, and R13 are used to adjust the battery conditioning current. The conditioning current
during over charge detection is given by Vcu (over charge detection voltage)/R (R: resistance). To
disable the conditioning function, open CD1, CD2, and CD3.
The over charge detection delay time (t
and over current detection delay time (t
the electrical characteristics.
R6 is a pull-up resistor that turns FET-B off when the COP terminal is opened. Connect a
100 kΩ to 1 MΩ resistor.
R5 is used to protect the IC if the charger is connected in reverse. Connect a 10 kΩ to 50 kΩ
resistor.
If capacitor C6 is absent, rush current occurs when a capacitive load is connected and the IC enters
the over current mode. C6 must be connected to prevent it.
If capacitor C5 is not connected, the IC may enter the over discharge condition due to variations of
battery voltage when the over current occurs. In this case, a charger must be connected to return
to the normal condition. To prevent this, connect an at least 0.01 µF capacitor to C5.
If a leak current flows between the delay capacitor connection terminal (CCT, CDT, or COVT) and
VSS, the delay time increases and an error occurs. The leak current must be 100 nA or less.
Over discharge detection can be disabled by using FET-C. The FET-C off leak must be 0.1 µA or
less. If over discharge is inhibited by using this FET, the current consumption does not fall below
0.1 µA even when the battery voltage drops and the IC enters the over discharge detection mode.
R1, R2, and R3 must be 1 kΩ or less.
R12
R13
R11
R1
R2
R3
C3
C2
C1
SS
), without R7 resistance is allowed .
FET1
FET2
FET3
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK
FET-A
VSS
VCC
CD1
VC1
CD2
VC2
CD3
Seiko Instruments Inc.
DOP
CU1
IOV1
Figure 9
FET-B
S-8233A series
Nch open
drain
) are changed with external capacitors (C4 to C6). See
to t
CU3
COP
), over discharge detection delay time (t
R6
1 MΩ
COVT
CCT
CTL
CDT
VMP
10 KΩ
R5
C4
C5
C6
GND: Normal operation
Floating: Inhibit charging
and discharging.
R7
Over charge delay
time setting
Over discharge delay
time setting
Over current delay
time setting
CC
CC
1 KΩ
EB+
voltage (ex. R7
EB-
voltage. Connect a
S-8233A Series
High: Inhibit over
FET-C
discharge
detection.
DD1
to t
DD3
19
),

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