CY7C63923-PVXC Cypress Semiconductor Corp, CY7C63923-PVXC Datasheet - Page 14
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CY7C63923-PVXC
Manufacturer Part Number
CY7C63923-PVXC
Description
IC USB PERIPHERAL CTRLR 48-SSOP
Manufacturer
Cypress Semiconductor Corp
Series
CY7Cr
Datasheet
1.CY7C63823-PXC.pdf
(68 pages)
Specifications of CY7C63923-PVXC
Controller Type
USB Peripheral Controller
Interface
USB
Voltage - Supply
4 V ~ 5.5 V
Current - Supply
40mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
48-SSOP
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
48
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
770-1001 - ISP 4PORT CYPRESS ENCORE II MCUCY4623 - KIT MOUSE REFERENCE DESIGN428-1774 - EXTENSION KIT FOR ENCORE II428-1773 - KIT DEVELOPMENT ENCORE II
Lead Free Status / RoHS Status
Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY7C63923-PVXC
Manufacturer:
CY
Quantity:
14
Part Number:
CY7C63923-PVXC
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
Document 38-08035 Rev. *E
9.2
The CY7C633xx/638xx/639xx microcontrollers provide up to
256 bytes of data RAM. In normal usage, the SRAM is parti-
tioned into two areas: stack, and user variables:
9.3
This section describes the Flash block of the enCoRe II. Much
of the user-visible Flash functionality including programming
and security are implemented in the M8C Supervisory Read
Only Memory (SROM).
9.3.1
All Flash programming is performed by code in the SROM. The
registers that control the Flash programming are only visible
to the M8C CPU when it is executing out of SROM. This makes
it impossible to read, write or erase the Flash by bypassing the
security mechanisms implemented in the SROM.
Customer firmware can only program the Flash via SROM
calls. The data or code images can be sourced via any
interface with the appropriate support firmware. This type of
programming requires a ‘boot-loader’—a piece of firmware
resident on the Flash. For safety reasons this boot-loader
should not be overwritten during firmware rewrites.
The Flash provides four extra auxiliary rows that are used to
hold Flash block protection flags, boot time calibration values,
configuration tables, and any device values. The routines for
accessing these auxiliary rows are documented in the SROM
section. The auxiliary rows are not affected by the device
erase function.
9.3.2
Most designs that include an enCoRe II part will have a USB
connector attached to the USB D+/D– pins on the device.
These designs require the ability to program or reprogram a
part through these two pins alone. The programming protocol
is not USB.
enCoRe II devices enable this type of in-system programming
by using the D+ and D– pins as the serial programming mode
interface. This allows an external controller to cause the
Top of RAM Memory
Data Memory Organization
Flash
Flash Programming and Security
In-System Programming
after reset
8-bit PSP
Figure 9-2. Data Memory Organization
Address
0xFF
0x00
Stack begins here and grows upward (user can modify)
The user determines the amount of memory needed for Stack
User Variables
enCoRe II part to enter serial programming mode and then to
use the test queue to issue Flash access functions in the
SROM.
9.4
The SROM holds code that is used to boot the part, calibrate
circuitry, and perform Flash operations. (Table 9-1 lists the
SROM functions.) The functions of the SROM may be
accessed in normal user code or operating from Flash. The
SROM exists in a separate memory space from user code.
The SROM functions are accessed by executing the Super-
visory System Call instruction (SSC), which has an opcode of
00h. Prior to executing the SSC the M8C’s accumulator needs
to be loaded with the desired SROM function code from
Table 9-1. Undefined functions will cause a HALT if called from
user code. The SROM functions are executing code with calls;
therefore, the functions require stack space. With the
exception of Reset, all of the SROM functions have a
parameter block in SRAM that must be configured before
executing the SSC. Table 9-2 lists all possible parameter block
variables. The meaning of each parameter, with regards to a
specific SROM function, is described later in this chapter.
Table 9-1. SROM Function Codes
Function Code
00h
01h
02h
03h
05h
06h
07h
SROM
Function Name
SWBootReset
EraseBlock
CheckSum
ReadBlock
WriteBlock
TableRead
EraseAll
CY7C63310
CY7C638xx
CY7C639xx
Stack Space
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