CY7C63923-PVXC Cypress Semiconductor Corp, CY7C63923-PVXC Datasheet - Page 26

• Manufacturer Part Number: CY7C63923-PVXC
• Description: IC USB PERIPHERAL CTRLR 48-SSOP
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C63923-PVXC

• Controller Type: USB Peripheral Controller
• Interface: USB
• Voltage - Supply: 4 V ~ 5.5 V
• Current - Supply: 40mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-SSOP
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1001 - ISP 4PORT CYPRESS ENCORE II MCUCY4623 - KIT MOUSE REFERENCE DESIGN428-1774 - EXTENSION KIT FOR ENCORE II428-1773 - KIT DEVELOPMENT ENCORE II
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant

Document 38-08035 Rev. *E
13.0
Table 13-1. Low-voltage Control Register (LVDCR) [0x1E3] [R/W]
13.0.1
Table 13-2. Voltage Monitor Comparators Register (VLTCMP) [0x1E4] [R]
This read-only register allows reading the current state of the Low-voltage-Detection and Precision-Power-On-Reset compar-
ators
Bit [7:2]: Reserved
Bit 1: LVD
This bit is set to indicate that the low-voltage-detect comparator has tripped, indicating that the supply voltage has gone below
the trip point set by VM[2:0] (See Table 13-1)
0 = No low-voltage-detect event
1= A low-voltage-detect has tripped
Bit 0: PPOR
This bit is set to indicate that the precision-power-on-reset comparator has tripped, indicating that the supply voltage is below
the trip point set by PORLEV[1:0]
0 = No precision-power-on-reset event
1= A precision-power-on-reset event has tripped
This register controls the configuration of the Power-on Reset / Low-voltage Detection block
Bit [7:6]: Reserved
Bit [5:4]: PORLEV[1:0]
This field controls the level below which the precision power-on-reset (PPOR) detector generates a reset
0 0 = 2.7V Range (trip near 2.6V)
0 1 = 3V Range (trip near 2.9V)
1 0 = 5V Range, >4.75V (trip near 4.65V)
1 1 = PPOR will not generate a reset, but values read from the Voltage Monitor Comparators Register (Table 13-2) give the
internal PPOR comparator state with trip point set to the 3V range setting
Bit 3: Reserved
Bit [2:0]: VM[2:0]
This field controls the level below which the low-voltage-detect trips—possibly generating an interrupt and the level at which the
Flash is enabled for operation.
Read/Write
Read/Write
VM[2:0]
Default
Default
Field
Field
Bit #
Bit #
000
001
010
100
101
011
110
111
POR Compare State
Low-voltage Detect Control
LVD Trip Point
(V) Min
2.69
2.90
3.00
3.11
4.46
4.61
4.70
4.78
7
–
0
7
–
0
Reserved
Point (V) Typ
LVD Trip
2.70
2.92
3.02
3.13
4.48
4.64
4.73
4.82
6
–
0
6
–
0
LVD Trip Point
(V) Max
5
–
0
2.72
2.94
3.04
3.15
4.51
4.67
4.76
4.85
R/W
5
0
Reserved
PORLEV[1:0]
4
–
0
R/W
4
0
Reserved
3
–
0
3
–
0
2
–
0
R/W
2
0
VM[2:0]
LVD
R
1
0
R/W
CY7C63310
CY7C638xx
CY7C639xx
1
0
Page 26 of 68
PPOR
R/W
R
0
0
0
0