CY7C63833-LFXC Cypress Semiconductor Corp, CY7C63833-LFXC Datasheet - Page 30

• Manufacturer Part Number: CY7C63833-LFXC
• Description: IC USB PERIPHERAL CTRLR 32VQFN
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C63833-LFXC

• Controller Type: USB Peripheral Controller
• Interface: USB
• Voltage - Supply: 4 V ~ 5.5 V
• Current - Supply: 40mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1001 - ISP 4PORT CYPRESS ENCORE II MCUCY4623 - KIT MOUSE REFERENCE DESIGN428-1774 - EXTENSION KIT FOR ENCORE II428-1773 - KIT DEVELOPMENT ENCORE II
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 428-2258; CY7C63833-LFXC

12.3 Low Power in Sleep Mode
To achieve the lowest possible power consumption during
suspend or sleep, the following conditions must be observed in
addition to considerations for the sleep timer:
All the other blocks go to the power down mode automatically on
suspend.
Document 38-08035 Rev. *K
1. All GPIOs must be set to outputs and driven low.
2. Clear P11CR[0], P10CR[0] - during USB and Non-USB opera-
3. Clear the USB Enable USBCR[7] - during USB mode opera-
4. Set P10CR[1] - during non-USB mode operations
5. Make sure 32 kHz oscillator clock is not selected as clock
tions
tions
source to ITMRCLK, TCAPCLK. Not even as clock output
source, onto either P01_CLKOUT or P12_VREG pins.
SAMPLE LVD/
LVD PPOR
BANDGAP
SAMPLE
ENABLE
CLK32K
CPUCLK/
SLEEP
24MHz
BRQ
BRA
CPU
POR
INT
PD
Sleep Timer or GPIO
(Not to Scale)
interrupt occurs
Figure 12-2. Wake Up Timing
32K clock and PD is negated to
Interrupt is double sampled by
The following steps are user configurable and help in reducing
the average suspend mode power consumption.
For low power considerations during sleep when external clock
is used as the CPUCLK source, the clock source must be held
low to avoid unintentional leakage current. If the clock is held
high, then there may be a leakage through M8C. To avoid current
consumption make sure ITMRCLK, TCPCLK, and USBCLK are
not sourced by either low power 32 kHz oscillator or 24 MHz
crystal-less oscillator. Do not select 24 MHz or 32 kHz oscillator
clocks on to the P01_CLKOUT/P12_VREG pin.
Note In case of a self powered designs, particularly battery
power, the USB suspend current specifications may not be met
because the USB pins are expecting termination.
1. Configure the power supply monitor at a large regular inter-
2. Configure the Low power oscillator into low power mode,
system
vals, control register bits are 1,EB[7:6] (Power system sleep
duty cycle PSSDC[1:0]).
control register bit is LOPSCTR[7].
CY7C63310, CY7C638xx
CPU is restarted after
90ms (nominal)
Page 30 of 83
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