CY7C63833-LFXC Cypress Semiconductor Corp, CY7C63833-LFXC Datasheet - Page 41

• Manufacturer Part Number: CY7C63833-LFXC
• Description: IC USB PERIPHERAL CTRLR 32VQFN
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C63833-LFXC

• Controller Type: USB Peripheral Controller
• Interface: USB
• Voltage - Supply: 4 V ~ 5.5 V
• Current - Supply: 40mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1001 - ISP 4PORT CYPRESS ENCORE II MCUCY4623 - KIT MOUSE REFERENCE DESIGN428-1774 - EXTENSION KIT FOR ENCORE II428-1773 - KIT DEVELOPMENT ENCORE II
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 428-2258; CY7C63833-LFXC

15.2 SPI Configure Register
Table 15-2. SPI Configure Register (SPICR) [0x3D] [R/W]
Table 15-3. SPI SCLK Frequency
Document 38-08035 Rev. *K
Bit 7: Swap
0 = Swap function disabled.
1 = The SPI block swaps its use of SMOSI and SMISO. This is useful in implementing single wire communications similar to SPI.
Bit 6: LSB First
0 = The SPI transmits and receives the MSB (Most Significant Bit) first.
1 = The SPI transmits and receives the LSB (Least Significant Bit) first.
Bit [5:4]: Comm Mode [1:0]
0 0: All SPI communication disabled.
0 1: SPI master mode
1 0: SPI slave mode
1 1: Reserved
Bit 3: CPOL
This bit controls the SPI clock (SCLK) idle polarity.
0 = SCLK idles low
1 = SCLK idles high
Bit 2: CPHA
The Clock Phase bit controls the phase of the clock on which data is sampled.
various combinations of LSB First, CPOL, and CPHA.
Bit [1:0]: SCLK Select
This field selects the speed of the master SCLK. When in master mode, SCLK is generated by dividing the base CPUCLK.
Note for Comm Modes 01b or 10b (SPI Master or SPI Slave)
When configured for SPI, (SPI Use = 1
automatically by the SPI logic. However, pin P1.4's input/output direction is NOT automatically set; it must be explicitly set by
firmware. For SPI Master mode, pin P1.4 must be configured as an output; for SPI Slave mode, pin P1.4 must be configured as
an input.
SCLK
Select
Read/Write
Default
00
01
10
11
Field
Bit #
CPUCLK
Divisor
12
48
96
6
Swap
R/W
7
0
12 MHz
2 MHz
1 MHz
250 kHz
125 kHz
SCLK Frequency when CPUCLK =
LSB First
R/W
6
0
Table 14-14
24 MHz
4 MHz
2 MHz
500 kHz
250 kHz
R/W
5
0
Comm Mode
on page 39), the input/output direction of pins P1.3, P1.5, and P1.6 is set
R/W
4
0
CPOL
R/W
3
0
Table 15-4
CPHA
R/W
on page 42 shows the timing for the
CY7C63310, CY7C638xx
2
0
R/W
1
0
SCLK Select
Page 41 of 83
R/W
0
0
[+] Feedback
[+] Feedback