DP83256VF National Semiconductor, DP83256VF Datasheet - Page 124
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DP83256VF
Manufacturer Part Number
DP83256VF
Description
IC FDDI LAYER CTRLR 160PQFP
Manufacturer
National Semiconductor
Series
PLAYER+™r
Datasheet
1.DP83256VF.pdf
(144 pages)
Specifications of DP83256VF
Controller Type
physical layer controller
Voltage - Supply
4.75 V ~ 5.25 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
160-BFQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Current - Supply
-
Interface
-
Other names
*DP83256VF
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7 0 Electrical Characteristics
AC Characteristics for the PMD Interface Outputs (ANSI Specifications)
The following output signals are covered PMD Request Data (PMRD) Transmit Clock (TXC) Recovered Data Out
(RXD OUT) Recovered Clock Out (RXC OUT)
Note The Alternate PMD Interface is only available on the 160 pin DP83257 PLAYER
enabled by the CGMREG TXCE bit The rest of the Alternate PMD Interface is enabled by the APMDREG APMDEN bit
Comments in square brackets are section references to the ANSI documents where these specifications can be found
Note 1 This parameter is not tested but is assured through characterization data and periodic testing of sample units
T57
T58
Symbol
PMRD Total Transmit Jitter
Data Dependent Jitter (DDJ)
Random Jitter (RJ)
Total Recovered Clock (RXC OUT) Jitter
Clock Data Dependent Jitter (C DDJ)
Random Jitter (C RJ)
Duty Cycle Distortion (DCD)
Static Alignment Error Accuracy (SAE)
Parameter
a
a
(Continued)
a
a
124
Conditions
(Note 1)
(Note 1)
PMD 8 1
PMD E 2
a
Device and the 100 pin DP83256-AP Device The Transmit Clock is
Min
Typ
Max
0 72
2 5
ns p-p
ns p-p
Units
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