DP83256VF National Semiconductor, DP83256VF Datasheet - Page 74

• Manufacturer Part Number: DP83256VF
• Description: IC FDDI LAYER CTRLR 160PQFP
• Manufacturer: National Semiconductor
• Series: PLAYER+™r

Specifications of DP83256VF

• Controller Type: physical layer controller
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 160-BFQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Supply: -
• Interface: -
• Other names: *DP83256VF

Bit
D0
D1
D2
D3
D4
D5
D6
D7
5 0 Registers
5 30 RECEIVE CONDITION COMPARISION REGISTER B (RCCRB)
The Receive Condition Comparison Register B ensures that the Control Bus must first read a bit modified by the PLAYER
device before it can be written to by the Control Bus Interface
The current state of RCRB is automatically written into the Receive Condition Comparison Register B (i e RCCRB
during a Control Bus Interface read cycle RCRB
During a Control Bus Interface write cycle the PLAYER
Condition Register (ICR) to 1 and prevent the setting or clearing of a bit within RCRB when the value of a bit in RCRB differs
from the value of the corresponding bit in the Receive Condition Comparison Register B
ACCESS RULES
RESC
ILSC
STC
ALSC
LSUPVC
CSEC
EBOUC
SILSC
RESC
Symbol
D7
ADDRESS
1Dh
IDLE LINE STATE COMPARISON The comparison bit for the Idle Line State bit (ILS) of the Receive Condition
Register B (RCRB)
STATE THRESHOLD COMPARISON The comparison bit for the State Threshold bit (ST) of the Receive
Condition Register B (RCRB)
ACTIVE LINE STATE COMPARISON The comparison bit for the Active Line State bit (ALS) of the Receive
Condition Register B (RCRB)
LINE STATE UNKNOWN AND PHY VALID COMPARISON The comparison bit for the Line State Unknown and
PHY Valid bit (LSUPV) of the Receive Condition Register B (RCRB)
CONNECTION SERVICE EVENT COMPARISON CASCADE SYNCHRONIZATION ERROR The comparison
bit for the Cascade Synchronization Error Connection Service Event bit (CSE) of the Receive Condition Register
B (RCRB)
ELASTICITY BUFFER OVERFLOW UNDERFLOW COMPARISON The comparison bit for the Elasticity Buffer
Overflow Underflow bit (EBOU) of the Receive Condition Register B (RCRB)
SUPER IDLE LINE STATE COMPARISON The comparison bit for the Super Idle Line State bit (SILS) of the
Receive Condition Register B (RCRB)
RESERVED COMPARISON The comparison bit for the Reserved bit (RES) of the Receive Condition Register B
(RCRB)
SILSC
D6
(Continued)
Always
READ
EBOUC
D5
CSEC
D4
WRITE
Always
a
LSUPVC
device will set the Conditional Write Inhibit bit (CWI) of the Interrupt
D3
74
Description
ALSC
D2
STC
D1
ILSC
D0
e
RCRB)
a