DP83256VF National Semiconductor, DP83256VF Datasheet - Page 53

• Manufacturer Part Number: DP83256VF
• Description: IC FDDI LAYER CTRLR 160PQFP
• Manufacturer: National Semiconductor
• Series: PLAYER+™r

Specifications of DP83256VF

• Controller Type: physical layer controller
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 160-BFQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Supply: -
• Interface: -
• Other names: *DP83256VF

D0
D1 D2
D3
D4-D7
5 0 Registers
5 9 CURRENT RECEIVE STATE REGISTER (CRSR)
The Current Receive State Register represents the current line state being detected by the Receiver Block When the Receiver
Block recognizes a new Line State the bits corresponding to the previous line state are cleared and the bits corresponding to
the new line state are set
During the reset process ( E RST
(LSU) is set to 1)
Note Users are discouraged from writing to this register An attempt to write into this register will cause the PLAYER
and set the Control Bus Write Command Reject bit (CCR) of the Interrupt Condition Register (ICR) to 1
ACCESS RULES
Bit
RES
ADDRESS
D7
LS0 LS1
LS2
LSU
RES
08h
Symbol
RES
D6
LINE STATE
Once the Receiver Block recognizes a new line state the bits corresponding to the previous line state are
cleared and the bits corresponding to the new line state are set
LS2
0
0
0
0
1
1
1
1
LINE STATE UNKNOWN The Receiver Block has not detected the minimum conditions to enter a known
line state When the Line State Unknown bit is set LS
RESERVED Reserved for future use
Note Users are discouraged from using these bits The reserved bits are reset to 0 during the reset process They may be set or cleared
(Continued)
Always
READ
without any effects to the functionality of the PLAYER
LS1
0
0
1
1
0
0
1
1
RES
D5
e
k
LS0
0
1
0
1
0
1
0
1
GND) the Receiver Block is forced to Line State Unknown (i e the Line State Unknown bit
0 1 2
Active Line State (ALS) Received a JK symbol pair (11000 10001) possibly followed
by data symbols
Idle Line State (ILS) Received a minimum of two consecutive Idle symbol pairs
(11111 11111)
No Signal Detect (NSD) The Signal Detect (SD) has been deasserted indicating that
the PLAYER
not being received from the Clock Recovery Module SD is ignored during internal
loopback
Note NSD is the default value when the device is in Stop mode However while in Stop mode certain data
Reserved Reserved for future use
Master Line State (MLS) Received a minimum of 8 consecutive Halt-Quiet symbol
pairs (00100 00000)
Halt Line State (HLS) Received a minimum of 8 consecutive Halt symbol pairs
(00100 00100)
Quiet Line State (QLS) Received a minimum of 8 consecutive Quiet symbol pairs
(00000 00000)
Noise Line State (NLS) Detected a minimum of 16 noise events Refer to the Receiver
Block description for further information on noise events
l
Write Reject
RES
WRITE
These bits represent the current Line State being detected by the Receiver Block
D4
patterns entering the Receiver Block may cause the PLAYER
either the NSD (010) or Reserved Value (011) during Stop mode
a
device is not receiving data from the PMD receiver or that clock detect is
LSU
D3
53
a
Description
device
LS2
D2
k
2 0
l
represent the most recently known line state
LS1
D1
a
device to ignore the Control Bus write cycle
a
to set LS0 Therefore the user may see
LS0
D0