DP83256VF National Semiconductor, DP83256VF Datasheet - Page 56

• Manufacturer Part Number: DP83256VF
• Description: IC FDDI LAYER CTRLR 160PQFP
• Manufacturer: National Semiconductor
• Series: PLAYER+™r

Specifications of DP83256VF

• Controller Type: physical layer controller
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 160-BFQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Supply: -
• Interface: -
• Other names: *DP83256VF

Bit
D0
D1
D2
D3
D4
D5
D6
D7
5 0 Registers
5 12 RECEIVE CONDITION MASK REGISTER A (RCMRA)
The Receive Condition Mask Register A allows the user to dynamically select which events will generate an interrupt
The Receive Condition A bit (RCA) of the Interrupt Condition Register (ICR) will be set to 1 when one or more bits within the
Receive Condition Register A (RCRA) is set to 1 and the corresponding mask bit(s) in this register is also set to 1
Since this register is cleared (i e set to 0) during the reset process all interrupts are initially masked
ACCESS RULES
LSUPIM
Symbol
NSDM
QLSM
HLSM
MLSM
NLSM
NTM
LSCM
LSUPIM
D7
ADDRESS
0Bh
NO SIGNAL DETECT MASK The mask bit for the No Signal Detect bit (NSD) of the Receive Condition Register A
(RCRA)
QUIET LINE STATE MASK The mask bit for the Quiet Line State bit (QLS) of the Receive Condition Register A
(RCRA)
HALT LINE STATE MASK The mask bit for the Halt Line State bit (HLS) of the Receive Condition Register A
(RCRA)
MASTER LINE STATE MASK The mask bit for the Master Line State bit (MLS) of the Receive Condition Register
A (RCRA)
NOISE LINE STATE MASK The mask bit for the Noise Line State bit (NLS) of the Receive Condition Register A
(RCRA)
NOISE THRESHOLD MASK The mask bit for the Noise Threshold bit (NT) of the Receive Condition Register A
(RCRA)
LINE STATE CHANGE MASK The mask bit for the Line State Change bit (LSC) of the Receive Condition
Register A (RCRA)
LINE STATE UNKNOWN AND PHY INVALID MASK The mask bit for the Line State Unknown and PHY Invalid
bit (LSUPI) of the Receive Condition Register A (RCRA)
LSCM
D6
(Continued)
Always
READ
NTM
D5
NLSM
D4
WRITE
Always
MLSM
D3
56
Description
HLSM
D2
QLSM
D1
NSDM
D0