DP83815CVNG National Semiconductor, DP83815CVNG Datasheet - Page 43

• Manufacturer Part Number: DP83815CVNG
• Description: IC CONTROLLER MEDIA ACCESS
• Manufacturer: National Semiconductor

Specifications of DP83815CVNG

• Controller Type: Ethernet Controller, MAC/BIU
• Interface: PCI
• Voltage - Supply: 3.3V
• Current - Supply: 170mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *DP83815CVNG

4.0 Register Set
Bit
10
9
8
7
6
5
4
3
2
1
0
EUPHCOMP DP83810 Descriptor Compatibility
BROM_DIS
Bit Name
PHY_RST
PHY_DIS
REQALG
PESEL
POW
BEM
EXD
SB
(Continued)
Reset internal Phy
Asserts reset to internal phy. Can be used to cause phy to reload options from the CFG register. This bit
does not self clear when set. R/W
Disable internal Phy
When set to a 1, this bit forces the internal phy to its low-power state. R/W
When set, DP83815 will use DP83810 compatible (but single fragment) descriptor format. Descriptors
are four 32-bit words in length, but the fragment count field is ignored. When clear, DP83815 will only
fetch 3 32-bit words in descriptor fetches with the third word being the fragment pointer. R/W
PCI Bus Request Algorithm
Selects mode for making requests for the PCI bus. When set to 0 (default), DP83815 will use an
aggressive Request scheme. When set to a 1, DP83815 will use a more conservative scheme. R/W
Single Back-off
Setting this bit to 1 forces the transmitter back-off state machine to always back-off for a single 802.3 slot
time instead of following the 802.3 random back-off algorithm. A 0 (default) allows normal transmitter
back-off operation. R/W
Program Out of Window Timer
This bit controls when the Out of Window collision timer begins counting its 512 bit slot time. A 0 causes
the timer to start after the SFD is received. A 1 causes the timer to start after the first bit of the preamble
is received. R/W
Excessive Deferral Timer disable
Setting this bit to 1 will inhibit transmit errors due to excessive deferral. This will inhibit the setting of the
ED status, and the logging of the TxExcessiveDeferral MIB counter. R/W
Parity Error Detection Action
This bit controls the assertion of SERR when a data parity error is detected while the DP83815 is acting
as the bus master. When set, parity errors will not result in the assertion of SERR. When reset, parity
errors will result in the assertion of SERR, indicating a system error. This bit should be set to a one by
software if the driver can handle recovery from and reporting of data parity errors. R/W
Disable Boot ROM interface
When set to 1, this bit inhibits the operation of the Boot ROM interface logic. R/W
Reserved
(reads return 0)
Big Endian Mode
When set, DP83815 will perform bus-mastered data transfers in “big endian” mode. Note that access to
register space is unaffected by the setting of this bit. R/W
43
Description
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