DP83815CVNG National Semiconductor, DP83815CVNG Datasheet - Page 46

• Manufacturer Part Number: DP83815CVNG
• Description: IC CONTROLLER MEDIA ACCESS
• Manufacturer: National Semiconductor

Specifications of DP83815CVNG

• Controller Type: Ethernet Controller, MAC/BIU
• Interface: PCI
• Voltage - Supply: 3.3V
• Current - Supply: 170mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *DP83815CVNG

4.0 Register Set
4.2.6 Interrupt Status Register
This register indicates the source of an interrupt when the INTA pin goes active. Enabling the corresponding bits in the
Interrupt Mask Register (IMR) allows bits in this register to produce an interrupt. When an interrupt is active, one or more
bits in this register are set to a “1”. The Interrupt Status Register reflects all current pending interrupts, regardless of the
state of the corresponding mask bit in the IMR. Reading the ISR clears all interrupts. Writing to the ISR has no effect.
31-26
19-17
Bit
25
24
23
22
21
20
16
15
14
13
12
11
10
9
8
Bit Name
TXRCMP
RXRCMP
RXSOVR
HIBERR
DPERR
RMABT
TXIDLE
SSERR
TXURN
TXERR
RTABT
PME
PHY
SWI
MIB
Offset: 0010h
(Continued)
Tag: ISR
Reserved
Transmit Reset Complete
Indicates that a requested transmit reset operation is complete.
Receive Reset Complete
Indicates that a requested receive reset operation is complete.
Detected Parity Error
This bit is set whenever CFGCS:DPERR is set, but cleared (like all other ISR bits) when the ISR register
is read.
Signaled System Error
The DP83815 signaled a system error on the PCI bus.
Received Master Abort
The DP83815 received a master abort generated as a result of target not responding.
Received Target Abort
The DP83815 received a target abort on the PCI bus.
unused
Rx Status FIFO Overrun
Set when an overrun condition occurs on the Rx Status FIFO.
High Bits Error Set
A logical OR of bits 25-16.
Phy interrupt
Set to 1 when internal phy generates an interrupt.
Power Management Event
Set when WOL conditioned detected.
Software Interrupt
Set whenever the SWI bit in the CR register is set.
MIB Service
Set when one of the enabled management statistics has reached its interrupt threshold. (See
Section 4.2.23)
Tx Underrun
Set when a transmit data FIFO underrun condition occurs.
Tx Idle
This event is signaled when the transmit state machine enters the idle state from a non-idle state. This
will happen whenever the state machine encounters an "end-of-list" condition (NULL link field or a
descriptor with OWN clear).
Tx Packet Error
This event is signaled after the last transmit descriptor in a failed transmission attempt has been updated
with valid status.
Access: Read Only
Size: 32 bits
46
Description
Hard Reset: 03008000h
Soft Reset: 03008000h
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