PIP202-12M-2 /T3 NXP Semiconductors, PIP202-12M-2 /T3 Datasheet - Page 4

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PIP202-12M-2 /T3

Manufacturer Part Number
PIP202-12M-2 /T3
Description
DC/DC Switching Converters TAPE7 MOSFET
Manufacturer
NXP Semiconductors
Datasheet

Specifications of PIP202-12M-2 /T3

Mounting Style
SMD/SMT
Package / Case
SOT-687
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
PIP202-12M-2,518
Philips Semiconductors
9397 750 11943
Product data
7.2 MOSFET driver function
7.3 Bootstrap diode
When the input voltage is LOW and current is flowing in the inductor, the upper
MOSFET must be off and the lower MOSFET must be on. Current flows from the
power ground (V
output.
Finally, when switching between states, both MOSFETs must not be on at the same
time.
The input, output and gate drive waveforms are shown in
voltage goes HIGH, the gate drive to the lower MOSFET immediately goes LOW. This
causes the output current to flow through the Schottky diode, connected between the
drain and source of the lower MOSFET. This causes output voltage to fall from zero to
approximately 0.5 V.
After a delay, if the input voltage is still HIGH, the gate drive to the upper MOSFET
goes HIGH. This causes the output voltage to rise to the output stage supply voltage,
V
When the input voltage goes LOW, the gate drive to the upper MOSFET immediately
goes LOW. The output voltage falls from V
diode at approximately 0.5 V.
After a delay, if the input voltage is still LOW, the gate drive to the lower MOSFET
goes HIGH. The lower MOSFET turns on, and the output voltage rises from 0.5 V to
zero.
A bootstrap diode is integrated into the design of the PIP202-12M between V
CB.
Fig 4. Input, output and gate drive waveforms of a synchronous DC-to-DC converter
DDO.
output stage.
Rev. 02 — 24 November 2003
SSO
upper MOSFET
lower MOSFET
), through the lower MOSFET and the inductor (L
output voltage
input voltage
gate drive
gate drive
DDO
delay
, until it is clamped by the Schottky
DC-to-DC converter powertrain
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
PIP202-12M-2
Figure
03ag35
delay
4. When the input
out
), to the
DDC
4 of 20
and

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