AD9959BCPZ Analog Devices Inc, AD9959BCPZ Datasheet - Page 4

• Manufacturer Part Number: AD9959BCPZ
• Description: IC DDS QUAD 10BIT DAC 56LFCSP
• Manufacturer: Analog Devices Inc

Specifications of AD9959BCPZ

• Resolution (bits): 10 b
• Design Resources: Phase Coherent FSK Modulator (CN0186)
• Master Fclk: 500MHz
• Tuning Word Width (bits): 32 b
• Voltage - Supply: 1.71 V ~ 1.96 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 56-LFCSP
• Sampling Rate: 500MSPS
• Input Channel Type: Serial
• Supply Voltage Range - Analog: 1.71V To 1.89V
• Supply Current: 160mA
• Digital Ic Case Style: CSP
• Data Interface: Serial, SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD9959
SPECIFICATIONS
AVDD and DVDD = 1.8 V ± 5%; DVDD_I/O = 3.3 V ± 5%; T = 25°C; R
(REFCLK multiplier bypassed), unless otherwise noted.
Table 1.
Parameter
REFERENCE CLOCK INPUT CHARACTERISTICS
DAC OUTPUT CHARACTERISTICS
WIDEBAND SFDR
NARROW-BAND SFDR
Resolution
Full-Scale Output Current
Gain Error
Channel-to-Channel Output Amplitude Matching Error
Output Current Offset
Differential Nonlinearity
Integral Nonlinearity
Output Capacitance
Voltage Compliance Range
Channel-to-Channel Isolation
1 MHz to 20 MHz Analog Output
20 MHz to 60 MHz Analog Output
60 MHz to 100 MHz Analog Output
100 MHz to 150 MHz Analog Output
150 MHz to 200 MHz Analog Output
1.1 MHz Analog Output (±10 kHz)
1.1 MHz Analog Output (±50 kHz)
1.1 MHz Analog Output (±250 kHz)
1.1 MHz Analog Output (±1 MHz)
15.1 MHz Analog Output (±10 kHz)
15.1 MHz Analog Output (±50 kHz)
15.1 MHz Analog Output (±250 kHz)
15.1 MHz Analog Output (±1 MHz)
40.1 MHz Analog Output (±10 kHz)
40.1 MHz Analog Output (±50 kHz)
40.1 MHz Analog Output (±250 kHz)
40.1 MHz Analog Output (±1 MHz)
75.1 MHz Analog Output (±10 kHz)
Frequency Range
REFCLK Multiplier Bypassed
REFCLK Multiplier Enabled
Internal VCO Output Frequency Range
Crystal REFCLK Source Range
Input Level
Input Voltage Bias Level
Input Capacitance
Input Impedance
Duty Cycle with REFCLK Multiplier Bypassed
Duty Cycle with REFCLK Multiplier Enabled
CLK Mode Select (Pin 24) Logic 1 Voltage
CLK Mode Select (Pin 24) Logic 0 Voltage
VCO Gain Control Bit Set High
VCO Gain Control Bit Set Low
1
1
Min
1
10
255
100
20
200
45
35
1.25
1.25
−
−2.5
AVDD − 0.50
65
10
Rev. B | Page 4 of 44
Typ
1.15
2
1500
1
±0.5
±1.0
3
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−82
−87
65
62
59
56
53
90
88
86
85
90
87
85
83
90
87
84
SET
= 1.91 kΩ; external reference clock frequency = 500 MSPS
Max
500
125
500
160
30
1000
55
65
1.8
0.5
10
10
+10
+2.5
25
AVDD + 0.50
Unit
MHz
MHz
MHz
MHz
MHz
mV
V
pF
Ω
%
%
V
V
Bits
mA
%FS
%
μA
LSB
LSB
pF
V
dB
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
Test Conditions/Comments
Measured at each pin (single-ended)
Must be referenced to AVDD
See Figure 34 and Figure 35
1.8 V digital input logic
1.8 V digital input logic
DAC supplies tied together
(see Figure 19)
The frequency range for wideband
SFDR is defined as dc to Nyquist