AD9959BCPZ Analog Devices Inc, AD9959BCPZ Datasheet - Page 7

IC DDS QUAD 10BIT DAC 56LFCSP

AD9959BCPZ

Manufacturer Part Number
AD9959BCPZ
Description
IC DDS QUAD 10BIT DAC 56LFCSP
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD9959BCPZ

Resolution (bits)
10 b
Design Resources
Phase Coherent FSK Modulator (CN0186)
Master Fclk
500MHz
Tuning Word Width (bits)
32 b
Voltage - Supply
1.71 V ~ 1.96 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
56-LFCSP
Sampling Rate
500MSPS
Input Channel Type
Serial
Supply Voltage Range - Analog
1.71V To 1.89V
Supply Current
160mA
Digital Ic Case Style
CSP
Data Interface
Serial, SPI
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

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Part Number
Manufacturer
Quantity
Price
Part Number:
AD9959BCPZ
Manufacturer:
ADI
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Part Number:
AD9959BCPZ
Manufacturer:
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Parameter
CMOS LOGIC OUTPUTS
POWER SUPPLY
DATA LATENCY (PIPELINE DELAY) SINGLE-TONE MODE
DATA LATENCY (PIPELINE DELAY) MODULATION MODE
DATA LATENCY (PIPELINE DELAY) LINEAR SWEEP MODE
1
2
3
4
For the VCO frequency range of 160 MHz to 255 MHz, there is no guarantee of operation.
Data latency is referenced to I/O_UPDATE.
Data latency is fixed.
Data latency is referenced to a profile change.
V
V
Total Power Dissipation—All Channels On,
Total Power Dissipation—All Channels On,
Total Power Dissipation—Full Power-Down
I
I
I
I
I
I
I
Frequency, Phase, and Amplitude Words to DAC
Frequency Word to DAC Output with Matched
Phase Offset Word to DAC Output with Matched
Amplitude Word to DAC Output with Matched
Frequency Word to DAC Output
Phase Offset Word to DAC Output
Amplitude Word to DAC Output
Frequency Rising/Falling Delta Tuning Word to DAC
Phase Offset Rising/Falling Delta Tuning Word to
Amplitude Rising/Falling Delta Tuning Word to DAC
AVDD
AVDD
DVDD
DVDD
DVDD_I/O
AVDD
DVDD
OH
OL
Single-Tone Mode
with Sweep Accumulator
Multiplier and 10-Bit Output Scalar Enabled
Multiplier and 10-Bit Output Scalar Enabled
Output with Matched Latency Enabled
Latency Disabled
Latency Disabled
Latency Disabled
Output
DAC Output
Output
—All Channels On, Single-Tone Mode
—All Channels On, Sweep Accumulator, REFCLK
—All Channels On, Single-Tone Mode
—All Channels On, Sweep Accumulator, REFCLK
Power-Down Mode
Power-Down Mode
2, 3
3
3
, 4
,
4
Min
21
2.7
29
29
25
17
34
29
41
37
29
Rev. B | Page 7 of 44
Typ
540
580
13
155
160
105
125
0.7
1.1
Max
0.4
635
680
180
185
125
145
40
30
Unit
V
V
mW
mW
mW
mA
mA
mA
mA
mA
mA
mA
mA
SYSCLK
s
SYSCLK
s
SYSCLK
s
SYSCLK
s
SYSCLK
s
SYSCLK
s
SYSCLK
s
SYSCLK
s
SYSCLK
s
SYSCLK
s
Test Conditions/Comments
1 mA load
Dominated by supply variation
Dominated by supply variation
I
I
DVDD
DVDD
= read
= write
AD9959

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