AD9910BSVZ Analog Devices Inc, AD9910BSVZ Datasheet - Page 48

• Manufacturer Part Number: AD9910BSVZ
• Description: IC DDS 1GSPS 14BIT PAR 100TQFP
• Manufacturer: Analog Devices Inc

Specifications of AD9910BSVZ

• Design Resources: Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121)
• Resolution (bits): 14 b
• Master Fclk: 1GHz
• Tuning Word Width (bits): 32 b
• Voltage - Supply: 1.8V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP Exposed Pad, 100-eTQFP, 100-HTQFP, 100-VQFP
• Pll Type: Frequency Synthesis
• Frequency: 1GHz
• Supply Current: 29mA
• Supply Voltage Range: 1.71V To 1.89V
• Digital Ic Case Style: TQFP
• No. Of Pins: 100
• Operating Temperature Range: -40°C To +85°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9910/PCBZ - BOARD EVAL FOR AD9910 1GSPS
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD9910
SERIAL PROGRAMMING
CONTROL INTERFACE—SERIAL I/O
The AD9910 serial port is a flexible, synchronous serial commu-
nications port allowing easy interface to many industry-standard
microcontrollers and microprocessors. The serial I/O is compatible
with most synchronous transfer formats.
The interface allows read/write access to all registers that configure
the AD9910. MSB-first or LSB-first transfer formats are supported.
In addition, the serial interface port can be configured as a single
pin input/output (SDIO) allowing a 2-wire interface, or it can
be configured as two unidirectional pins for input/output
(SDIO/SDO) enabling a 3-wire interface. Two optional pins
(I/O_RESET and CS ) enable greater flexibility for designing
systems with the AD9910.
GENERAL SERIAL I/O OPERATION
There are two phases to a serial communications cycle. The first
is the instruction phase to write the instruction byte into the
AD9910. The instruction byte contains the address of the register
to be accessed (see the Register Map and Bit Descriptions
section) and defines whether the upcoming data transfer is a
write or read operation.
For a write cycle, Phase 2 represents the data transfer between
the serial port controller to the serial port buffer. The number
of bytes transferred is a function of the register being accessed.
For example, when accessing the Control Function Register 2
(Address 0x01), Phase 2 requires that four bytes be transferred.
Each bit of data is registered on each corresponding rising edge
of SCLK. The serial port controller expects that all bytes of the
register be accessed; otherwise, the serial port controller is put
out of sequence for the next communication cycle. However,
one way to write fewer bytes than required is to use the I/O_RESET
pin feature. The I/O_RESET pin function can be used to abort
an I/O operation and reset the pointer of the serial port con-
troller. After an I/O reset, the next byte is the instruction byte.
Note that every completed byte written prior to an I/O reset is
preserved in the serial port buffer. Partial bytes written are not
preserved. At the completion of any communication cycle, the
AD9910 serial port controller expects the next eight rising
SCLK edges to be the instruction byte for the next communi-
cation cycle.
After a write cycle, the programmed data resides in the serial
port buffer and is inactive. I/O_UPDATE transfers data from
the serial port buffer to active registers. The I/O update can be
sent either after each communication cycle or when all serial
operations are complete. In addition, a change in profile pins
can initiate an I/O update.
For a read cycle, Phase 2 is the same as the write cycle with the
following differences: data is read from the active registers, not
the serial port buffer, and data is driven out on the falling edge
of SCLK.
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Note that to read back any profile register (0x0E to 0x15), the
three external profile pins must be used. For example, if the
profile register is Profile 5 (0x13), then the PROFILE[0:2] pins
must equal 101.This is not required to write to profile registers.
INSTRUCTION BYTE
The instruction byte contains the following information as
shown in the instruction byte information bit map.
Instruction Byte Information Bit Map
MSB
D7
R/W
R/ W —Bit 7 of the instruction byte determines whether a read
or write data transfer occurs after the instruction byte write.
Logic 1 indicates a read operation. Cleared indicates a write
operation.
X, X—Bit 6 and Bit 5 of the instruction byte are don’t cares.
A4, A3, A2, A1, A0—Bit 4, Bit 3, Bit 2, Bit 1, and Bit 0 of the
instruction byte determine which register is accessed during the
data transfer portion of the communications cycle.
SERIAL I/O PORT PIN DESCRIPTIONS
SCLK—Serial Clock
The serial clock pin is used to synchronize data to and from the
AD9910 and to run the internal state machines.
CS —Chip Select Bar
CS is an active low input that allows more than one device on
the same serial communications line. The SDO and SDIO pins
go to a high impedance state when this input is high. If driven
high during any communications cycle, that cycle is suspended
until CS is reactivated low. Chip select ( CS ) can be tied low in
systems that maintain control of SCLK.
SDIO—Serial Data Input/Output
Data is always written into the AD9910 on this pin. However,
this pin can be used as a bidirectional data line. Bit 1 of CFR1
Register Address 0x00 controls the configuration of this pin.
The default is cleared, which configures the SDIO pin as
bidirectional.
SDO—Serial Data Out
Data is read from this pin for protocols that use separate lines
for transmitting and receiving data. When the AD9910 operates
in single bidirectional I/O mode, this pin does not output data
and is set to a high impedance state.
D6
X
D5
X
D4
A4
D3
A3
D2
A2
A1
D1
LSB
D0
A0