CY7C68001-56PVXC Cypress Semiconductor Corp, CY7C68001-56PVXC Datasheet - Page 25

• Manufacturer Part Number: CY7C68001-56PVXC
• Description: IC USB INTERFACE SX2 56-SSOP
• Manufacturer: Cypress Semiconductor Corp
• Type: USBr
• Series: CY7Cr

Specifications of CY7C68001-56PVXC

• Package / Case: 56-SSOP
• Protocol: USB 2.0
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: 0 C to + 70 C
• Operating Supply Voltage: 3.3 V
• Core Size: 8 Bit
• No. Of I/o's: 35
• Ram Memory Size: 256Byte
• Embedded Interface Type: SPI, USB
• Digital Ic Case Style: SSOP
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-1864; CY7C68001-56PVXC

13.2 Command Interface
Table 13-1. Command Synchronous Read Parameters with Internally Sourced IFCLK
Document #: 38-08013 Rev. *J
t
t
t
t
t
t
IFCLK
SRD
RDH
OEon
OEoff
INT
Table 13-2. Command Synchronous Read with Externally Sourced IFCLK
Notes
t
t
t
t
t
t
IFCLK
SRD
RDH
OEon
OEoff
INT
13. Dashed lines denote signals with programmable polarity.
14. Externally sourced IFCLK must not exceed 50 MHz.
Parameter
Parameter
IFCLK period
SLRD to Clock Setup Time
Clock to SLRD Hold Time
SLOE Turn on to FIFO Data Valid
SLOE Turn off to FIFO Data Hold
Clock to INT# Output Propagation Delay
IFCLK Period
SLRD to Clock Setup Time
Clock to SLRD Hold Time
SLOE Turn on to FIFO Data Valid
SLOE Turn off to FIFO Data Hold
Clock to INT# Output Propagation Delay
IFCLK
SLRD
DATA
SLOE
INT#
Figure 13-1. Command Synchronous Read Timing Diagram
Description
Description
t
OEon
t
SRD
t
IFCLK
t
INT
N
t
RDH
[14]
20.83
18.7
Min
t
OEoff
12.7
Min
0
3.7
20
[13]
Max
10.5
10.5
9.5
Max
10.5
13.5
10.5
200
CY7C68001
Page 25 of 45
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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