CY7C68001-56PVXC Cypress Semiconductor Corp, CY7C68001-56PVXC Datasheet - Page 6

• Manufacturer Part Number: CY7C68001-56PVXC
• Description: IC USB INTERFACE SX2 56-SSOP
• Manufacturer: Cypress Semiconductor Corp
• Type: USBr
• Series: CY7Cr

Specifications of CY7C68001-56PVXC

• Package / Case: 56-SSOP
• Protocol: USB 2.0
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: 0 C to + 70 C
• Operating Supply Voltage: 3.3 V
• Core Size: 8 Bit
• No. Of I/o's: 35
• Ram Memory Size: 256Byte
• Embedded Interface Type: SPI, USB
• Digital Ic Case Style: SSOP
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-1864; CY7C68001-56PVXC

The SX2 accepts either an internally derived clock (30 MHz or
48 MHz) or externally supplied clock (IFCLK, 5 to 50 MHz), and
SLRD, SLWR, SLOE, PKTEND, CS#, FIFOADR[2:0] signals
from an external master. The interface can be selected for 8- or
16- bit operation by an internal configuration bit, and an Output
Enable signal SLOE enables the data bus driver of the selected
width. The external master must ensure that the output enable
signal is inactive when writing data to the SX2. The interface can
operate either asynchronously where the SLRD and SLWR
signals act directly as strobes, or synchronously where the SLRD
and SLWR act as clock qualifiers. The optional CS# signal
tristates the data bus and ignore SLRD, SLWR, PKTEND.
The external master reads from OUT endpoints and writes to IN
endpoints, and reads from or writes to the command interface.
Read: SLOE and SLRD
In synchronous mode, the FIFO pointer is incremented on each
rising edge of IFCLK while SLRD is asserted. In asynchronous
mode,
asserted-to-deasserted transition of SLRD.
SLOE is a data bus driver enable. When SLOE is asserted, the
data bus is driven by the SX2.
Write: SLWR
In synchronous mode, data on the FD bus is written to the FIFO
(and the FIFO pointer is incremented) on each rising edge of
IFCLK while SLWR is asserted. In asynchronous mode, data on
the FD bus is written to the FIFO (and the FIFO pointer is incre-
mented) on each asserted-to-deasserted transition of SLWR.
PKTEND
PKTEND commits the current buffer to USB. To send a short IN
packet (one which has not been filled to max packet size deter-
mined by the value of PL[X:0] in EPxPKTLENH/L), the external
master strobes the PKTEND pin.
All these interface signals have a default polarity of low. In order
to change the polarity of PKTEND pin, the master may write to
the POLAR register anytime. In order to switch the polarity of the
SLWR/SLRD/SLOE, the master must set the appropriate bits 2,
3 and 4 respectively in the FIFOPINPOLAR register located at
XDATA space 0xE609. Please note that the SX2 powers up with
the polarities set to low.
provides further information on how to access this register
located at XDATA space.
5.7.3 IFCLK
The IFCLK pin can be configured to be either an input (default)
or an output interface clock. Bits IFCONFIG[7:4] define the
behavior of the interface clock. To use the SX2’s inter-
nally-derived 30- or 48 MHz clock, set IFCONFIG.7 to 1 and set
IFCONFIG.6 to 0 (30 MHz) or to 1 (48 MHz). To use an externally
supplied clock, set IFCONFIG.7=0 and drive the IFCLK pin
(5 MHz to 50 MHz). The input or output IFCLK signal can be
inverted by setting IFCONFIG.4=1.
Document #: 38-08013 Rev. *J
Note
4. In indexed mode, the value of the FLAGx pins is indeterminate except when addressing a FIFO (FIFOADR[2:0]={000,001,010,011}).
the
FIFO
pointer
POLAR Register 0x04
is
incremented
on page 18
on
each
5.7.4 FIFO Access
An external master can access the slave FIFOs either asynchro-
nously or synchronously:
■
■
An external master accesses the FIFOs through the data bus,
FD [15:0]. This bus can be either 8- or 16-bits wide; the width is
selected via the WORDWIDE bit in the EPxPKTLENH/L
registers. The data bus is bidirectional, with its output drivers
controlled by the SLOE pin. The FIFOADR[2:0] pins select which
of the four FIFOs is connected to the FD [15:0] bus, or if the
command interface is selected.
5.7.5 FIFO Flag Pins Configuration
The FIFO flags are FLAGA, FLAGB, FLAGC, and FLAGD.
These FLAGx pins report the status of the FIFO selected by the
FIFOADR[2:0] pins. At reset, these pins are configured to report
the status of the following:
■
■
■
■
The FIFO flags can either be indexed or fixed. Fixed flags report
the status of a particular FIFO regardless of the value on the
FIFOADR [2:0] pins. Indexed flags report the status of the FIFO
selected by the FIFOADR [2:0]pins.
5.7.6 Default FIFO Programmable Flag Setup
By default, FLAGA is the Programmable Flag (PF) for the
endpoint being pointed to by the FIFOADR[2:0] pins. For EP2
and EP4, the default endpoint configuration is BULK, OUT, 512,
2x; the PF pin asserts when the entire FIFO has ≥ 512 bytes. For
EP6 and EP8, the default endpoint configuration is BULK, IN,
512, 2x, and the PF pin asserts when the entire FIFO has less
than/equal to 512 bytes. In other words, EP6/8 report a
half-empty state, and EP2/4 report a half-full state.
5.7.7 FIFO Programmable Flag (PF) Setup
Each FIFO’s programmable-level flag (PF) asserts when the
FIFO reaches a user-defined fullness threshold. That threshold
is configured as follows:
1. For OUT packets: The threshold is stored in PFC12:0. The PF
2. For IN packets, with PKTSTAT = 1: The threshold is stored in
3. For IN packets, with PKTSTAT = 0: The threshold is stored in
Asynchronous–SLRD, SLWR, and PKTEND pins are strobes.
Synchronous–SLRD, SLWR, and PKTEND pins are enables
for the IFCLK clock pin.
FLAGA reports the status of the programmable flag.
FLAGB reports the status of the full flag.
FLAGC reports the status of the empty flag.
FLAGD defaults to the CS# function.
is asserted when the number of bytes in the entire FIFO is
less than/equal to (DECIS = 0) or greater than/equal to (DE-
CIS = 1) the threshold.
PFC9:0. The PF is asserted when the number of bytes written
into the current packet in the FIFO is less than/equal to
(DECIS = 0) or greater than/equal to (DECIS = 1) the
threshold.
two parts: PKTS2:0 holds the number of committed packets,
and PFC9:0 holds the number of bytes in the current packet.
The PF is asserted when the FIFO is at or less full than
(DECIS = 0), or at or more full than (DECIS = 1), the threshold.
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CY7C68001
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