DP83849CVS/NOPB National Semiconductor, DP83849CVS/NOPB Datasheet - Page 70

• Manufacturer Part Number: DP83849CVS/NOPB
• Description: IC TXRX ETHERNET PHY DUAL 80TQFP
• Manufacturer: National Semiconductor
• Type: Transceiverr

Specifications of DP83849CVS/NOPB

• Number Of Drivers/receivers: 2/2
• Protocol: Ethernet
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 80-TQFP, 80-VQFP
• Data Rate: 100Mbps
• Supply Voltage Range: 3V To 3.6V
• Logic Case Style: TQFP
• No. Of Pins: 80
• Operating Temperature Range: 0°C To +70°C
• Msl: MSL 3 - 168 Hours
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Data Rate Max: 10Mbps
• For Use With: DP83849CVS-EVK - BOARD EVALUATION DP83849CVS
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *DP83849CVS; *DP83849CVS/NOPB; DP83849CVS

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7.3 Link Diagnostics Registers - Page 2
Page 2 Link Diagnostics Registers are accessible by setting bits [1:0] = 10 of PAGESEL (13h).
7.3.1
This register contains linked cable length estimation in 100Mb operation. The cable length is an estimation of the effec-
tive cable length based on the characteristics of the recovered signal. The cable length is valid only during 100Mb oper-
ation with a valid Link status indication.
7.3.2
This register returns an indication of clock frequency offset relative to the link partner. Two values can be read, the long
term Frequency Offset, or a short term Frequency Control value. The Frequency Control value includes short term
phase correction. The variance between the Frequency Control value and the Frequency Offset can be used as an indi-
cation of the amount of jitter in the system
15:8
14:9
Bit
7:0
Bit
7:0
15
8
100Mb Length Detect Register (LEN100_DET), Page 2, address 14h
100Mb Frequency Offset Indication Register (FREQ100), Page 2, address 15h
SAMPLE_FREQ
FREQ_OFFSET
CABLE_LEN
RESERVED
RESERVED
Table 44. 100Mb Frequency Offset Indication Register (FREQ100), address 15h
Bit Name
Bit Name
SEL_FC
Table 43. 100Mb Length Detect Register (
Default
Default
0, RW
0, RW
0, RO
0, RO
0, RO
0, RO
.
RESERVED: Writes ignored, read as 0.
Cable Length Estimate:
Indicates an estimate of effective cable length in meters. A value
of FF indicates cable length cannot be determined.
Sample Frequency Offset:
If Sel_FC is set to a 0, then setting this bit to a 1 will poll the DSP
for the long-term Frequency Offset value. The value will be avail-
able in the Freq_Offset bits of this register.
If Sel_FC is set to a 1, then setting this bit to a 1 will poll the DSP
for the current Frequency Control value. The value will be available
in the Freq_Offset bits of this register.
This register bit will always read back as 0.
RESERVED: Writes ignored, read as 0.
Select Frequency Control:
Setting this bit to a 1 will select the current Frequency Control value
instead of the Frequency Offset. This value contains Frequency
Offset plus the short term phase correction and can be used to in-
dicate amount of jitter in the system. The value will be available in
the Freq_Offset bits of this register.
Frequency Offset:
Frequency offset value loaded from the DSP following assertion of
the Sample_Freq control bit. The Frequency Offset or Frequency
Control value is a twos-complement signed value in units of ap-
proximately 5.1562ppm. The range is as follows:
0x7F = +655ppm
0x00 = 0ppm
0x80 = -660ppm
70
LEN100_DET
Description
Description
), address 14h