PIC18F2550-I/SP Microchip Technology Inc., PIC18F2550-I/SP Datasheet - Page 126

• Manufacturer Part Number: PIC18F2550-I/SP
• Description: Microcontroller; 32 KB Flash; 2048 RAM; 256 EEPROM; 24 I/O; 28-Pin-SPDIP
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F2550-I/SP

• A/d Inputs: 10-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 12 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 23
• Interface: I2C/SPI/USART/USB
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 32K Bytes
• Ram Size: 2K Bytes
• Speed: 48 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F2455/2550/4455/4550
TABLE 10-9:
TABLE 10-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
DS39632C-page 124
PORTE
LATE
TRISE
ADCON1
CMCON
SPPCON
SPPCFG
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTE.
Note 1:
RE0/AN5/
CK1SPP
RE1/AN6/
CK2SPP
RE2/AN7/
OESPP
MCLR/V
RE3
Legend:
Note 1:
Name
Pin
(3)
2:
3:
(3)
PP
(3)
(3)
/
Implemented only when Master Clear functionality is disabled (MCLRE Configuration bit = 0).
RE3 is the only PORTE bit implemented on both 28-pin and 40/44-pin devices. All other bits are
implemented only when PORTE is implemented (i.e., 40/44-pin devices).
These registers or bits are unimplemented on 28-pin devices.
OUT = Output, IN = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input
RE3 does not have a corresponding TRISE<3> bit. This pin is always an input regardless of mode.
CLKCFG1 CLKCFG0
RDPU
C2OUT
Bit 7
Function
CK1SPP
CK2SPP
—
—
—
—
OESPP
PORTE I/O SUMMARY
MCLR
RE0
AN5
RE1
AN6
RE2
AN7
RE3
V
(3)
PP
C1OUT
Bit 6
Setting
—
—
—
—
—
TRIS
—
—
—
0
1
1
0
0
1
1
0
0
1
1
0
(1)
(1)
(1)
VCFG1
C2INV
CSEN
OUT
OUT
OUT
OUT
OUT
OUT
Bit 5
I/O
IN
IN
IN
IN
IN
IN
IN
IN
IN
—
—
—
—
I/O Type
ANA
ANA
ANA
ANA
DIG
DIG
DIG
DIG
DIG
DIG
ST
ST
ST
ST
ST
CLK1EN
VCFG0
C1INV
Preliminary
Bit 4
—
—
—
—
LATE<0> data output; not affected by analog input.
PORTE<0> data input; disabled when analog input enabled.
A/D input channel 5; default configuration on POR.
SPP clock 1 output (SPP enabled).
LATE<1> data output; not affected by analog input.
PORTE<1> data input; disabled when analog input enabled.
A/D input channel 6; default configuration on POR.
SPP clock 2 output (SPP enabled).
LATE<2> data output; not affected by analog input.
PORTE<2> data input; disabled when analog input enabled.
A/D input channel 7; default configuration on POR.
SPP enable output (SPP enabled).
External Master Clear input; enabled when MCLRE Configuration bit
is set.
High-voltage detection, used for ICSP™ mode entry detection.
Always available regardless of pin mode.
PORTE<3> data input; enabled when MCLRE Configuration bit is
clear.
RE3
PCFG3
Bit 3
WS3
CIS
—
—
—
(1,2)
TRISE2
PCFG2
LATE2
RE2
Bit 2
WS2
CM2
—
(3)
Description
SPPOWN
TRISE1
PCFG1
RE1
LATE1
Bit 1
CM1
WS1
© 2006 Microchip Technology Inc.
(3)
TRISE0
PCFG0
SPPEN
RE0
LATE0
Bit 0
CM0
WS0
(3)
on page
Values
Reset
54
54
54
52
53
55
55