PIC18F2550-I/SP Microchip Technology Inc., PIC18F2550-I/SP Datasheet - Page 128
PIC18F2550-I/SP
Manufacturer Part Number
PIC18F2550-I/SP
Description
Microcontroller; 32 KB Flash; 2048 RAM; 256 EEPROM; 24 I/O; 28-Pin-SPDIP
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F2550-ISP.pdf
(430 pages)
Specifications of PIC18F2550-I/SP
A/d Inputs
10-Channel, 10-Bit
Comparators
2
Cpu Speed
12 MIPS
Eeprom Memory
256 Bytes
Input Output
23
Interface
I2C/SPI/USART/USB
Memory Type
Flash
Number Of Bits
8
Package Type
28-pin SPDIP
Programmable Memory
32K Bytes
Ram Size
2K Bytes
Speed
48 MHz
Timers
1-8-bit, 3-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
Available stocks
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Quantity
Price
Company:
Part Number:
PIC18F2550-I/SP
Manufacturer:
MICROCHIP
Quantity:
2 100
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PIC18F2455/2550/4455/4550
11.1
Timer0 can operate as either a timer or a counter; the
mode
(T0CON<5>). In Timer mode, the module increments
on every clock by default unless a different prescaler
value is selected (see Section 11.3 “Prescaler”). If
the TMR0 register is written to, the increment is
inhibited for the following two instruction cycles. The
user can work around this by writing an adjusted value
to the TMR0 register.
The Counter mode is selected by setting the T0CS bit
(= 1). In Counter mode, Timer0 increments either on
every rising or falling edge of pin RA4/T0CKI. The
incrementing edge is determined by the Timer0 Source
Edge Select bit, T0SE (T0CON<4>); clearing this bit
selects the rising edge. Restrictions on the external
clock input are discussed below.
An external clock source can be used to drive Timer0;
however, it must meet certain requirements to ensure
that the external clock can be synchronized with the
FIGURE 11-1:
FIGURE 11-2:
DS39632C-page 126
Note:
T0CKI pin
is
Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI maximum prescale.
T0CKI pin
Timer0 Operation
Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI maximum prescale.
selected
T0SE
T0CS
T0PS2:T0PS0
PSA
F
OSC
T0SE
T0CS
T0PS2:T0PS0
PSA
/4
F
OSC
TIMER0 BLOCK DIAGRAM (8-BIT MODE)
TIMER0 BLOCK DIAGRAM (16-BIT MODE)
by
/4
0
1
clearing
0
1
Programmable
Prescaler
the
Programmable
3
Prescaler
T0CS
3
1
0
Preliminary
bit
1
0
(2 T
Sync with
Internal
Clocks
CY
(2 T
Delay)
Sync with
Internal
Clocks
internal phase clock (T
synchronization and the onset of incrementing the
timer/counter.
11.2
TMR0H is not the actual high byte of Timer0 in 16-bit
mode. It is actually a buffered version of the real high
byte of Timer0 which is not directly readable nor
writable (refer to Figure 11-2). TMR0H is updated with
the contents of the high byte of Timer0 during a read of
TMR0L. This provides the ability to read all 16 bits of
Timer0 without having to verify that the read of the high
and low byte were valid, due to a rollover between
successive reads of the high and low byte.
Similarly, a write to the high byte of Timer0 must also
take place through the TMR0H Buffer register. The high
byte is updated with the contents of TMR0H when a
write occurs to TMR0L. This allows all 16 bits of Timer0
to be updated at once.
CY
Delay)
Timer0 Reads and Writes in
16-Bit Mode
TMR0L
8
8
TMR0L
8
OSC
8
© 2006 Microchip Technology Inc.
High Byte
TMR0H
TMR0
8
). There is a delay between
8
Set
TMR0IF
on Overflow
Internal Data Bus
8
Set
TMR0IF
on Overflow
Read TMR0L
Write TMR0L
Internal Data Bus
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