PIC18F2550-I/SP Microchip Technology Inc., PIC18F2550-I/SP Datasheet - Page 210
PIC18F2550-I/SP
Manufacturer Part Number
PIC18F2550-I/SP
Description
Microcontroller; 32 KB Flash; 2048 RAM; 256 EEPROM; 24 I/O; 28-Pin-SPDIP
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F2550-ISP.pdf
(430 pages)
Specifications of PIC18F2550-I/SP
A/d Inputs
10-Channel, 10-Bit
Comparators
2
Cpu Speed
12 MIPS
Eeprom Memory
256 Bytes
Input Output
23
Interface
I2C/SPI/USART/USB
Memory Type
Flash
Number Of Bits
8
Package Type
28-pin SPDIP
Programmable Memory
32K Bytes
Ram Size
2K Bytes
Speed
48 MHz
Timers
1-8-bit, 3-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
Available stocks
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PIC18F2455/2550/4455/4550
19.4.3.2
Masking an address bit causes that bit to become a
“don’t care”. When one address bit is masked, two
addresses will be Acknowledged and cause an
interrupt. It is possible to mask more than one address
bit at a time, which makes it possible to Acknowledge
up to 31 addresses in 7-bit mode and up to 63
addresses in 10-bit mode (see Example 19-2).
The I
masking is used or not. However, when address
masking is used, the I
multiple addresses and cause interrupts. When this
occurs, it is necessary to determine which address
caused the interrupt by checking SSPBUF.
In
ADMSK<5:1> (SSPCON2<5:1>) mask the corre-
sponding address bits in the SSPADD register. For any
ADMSK bits that are set (ADMSK<n> = 1), the
corresponding
(SSPADD<n> = x). For the module to issue an address
Acknowledge, it is sufficient to match only on
addresses that do not have an active address mask.
EXAMPLE 19-2:
DS39632C-page 208
7-bit addressing:
10-bit addressing:
7-Bit
2
C Slave behaves the same way whether address
SSPADD<7:1> = A0h (1010000) (SSPADD<0> is assumed to be ‘0’)
ADMSK<5:1>
Addresses Acknowledged : A0h, A2h, A4h, A6h, A8h, AAh, ACh, AEh
SSPADD<7:0> = A0h (10100000) (The two MSbs of the address are ignored in this example, since
they are not affected by masking)
ADMSK<5:1>
Addresses Acknowledged: A0h, A1h, A2h, A3h, A4h, A5h, A6h, A7h, A8h, A9h, AAh, ABh, ACh, ADh,
AEh, AFh
Address
Address Masking
address
ADDRESS MASKING EXAMPLES
mode,
= 00111
= 00111
2
C slave can Acknowledge
address
bit
is
mask
ignored
Preliminary
bits
In 10-Bit Address mode, bits ADMSK<5:2> mask the
corresponding address bits in the SSPADD register. In
addition, ADMSK1 simultaneously masks the two LSbs
of the address (SSPADD<1:0>). For any ADMSK bits
that are active (ADMSK<n> = 1), the corresponding
address bit is ignored (SSPADD<n> = x). Also note
that although in 10-Bit Addressing mode, the upper
address bits reuse part of the SSPADD register bits, the
address mask bits do not interact with those bits. They
only affect the lower address bits.
Note 1: ADMSK1 masks the two Least Significant
2: The two Most Significant bits of the
bits of the address.
address are not affected by address
masking.
© 2006 Microchip Technology Inc.
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