DS2154L+ Maxim Integrated Products, DS2154L+ Datasheet
DS2154L+
Specifications of DS2154L+
Related parts for DS2154L+
DS2154L+ Summary of contents
Page 1
... For information about device errata, click here: www.maxim-ic.com/errata. Enhanced E1 Single-Chip Transceiver PIN CONFIGURATION TOP VIEW 1 (14mm x 14mm) ORDERING INFORMATION PART DS2154L 0°C to +70°C DS2154L+ 0°C to +70°C DS2154LN -40°C to +85°C DS2154LN+ -40°C to +85°C + Denotes lead-free/RoHS-compliant package DS2154 ...
Page 2
DETAILED DESCRIPTION....................................................................................................6 1.1 I ............................................................................................................................. 6 NTRODUCTION 1.1.1 New Features......................................................................................................................................... 6 1 UNCTIONAL ESCRIPTION 1.3 R ’ N ........................................................................................................................... 7 EADER S OTE 2 PIN DESCRIPTION................................................................................................................9 2 RANSMIT IDE IGITAL 2 ...
Page 3
LINE INTERFACE FUNCTION .......................................................................................63 13 ECEIVE LOCK AND 13 RANSMIT AVESHAPING AND 13 ITTER TTENUATOR 14 TIMING DIAGRAMS ....................................................................................................... CHARACTERISTICS................................................................................................ CHARACTERISTICS................................................................................................77 17 PACKAGE INFORMATION ............................................................................................87 17.1 100-P LQFP (56-G5002-000)................................................................................................. ...
Page 4
Figure 1-1. DS2154 Enhanced E1 Single-Chip Transceiver ...................................................................... 8 Figure 13-1. External Analog Connections............................................................................................... 66 Figure 13-2. Jitter Tolerance .................................................................................................................... 67 Figure 13-3. Transmit Waveform Template .............................................................................................. 67 Figure 13-4. Jitter Attenuation .................................................................................................................. 68 Figure 14-1. Receive Side Timing ............................................................................................................ ...
Page 5
Table 2-1. Register Map ........................................................................................................................... 15 Table 4-1. Sync/Resync Criteria............................................................................................................... 21 Table 5-1. Alarm Criteria .......................................................................................................................... 35 Table 13-1. Line Build-Out Select in LICR................................................................................................ 64 Table 13-2. Transformer Specifications.................................................................................................... 65 Table 15-1. Recommended DC Operating Conditions ............................................................................. 76 Table 15-2. ...
Page 6
DETAILED DESCRIPTION The DS2154 enhanced single-chip transceiver (SCT) contains all the necessary functions for connection to E1 lines. The device is an upward compatible version of the DS2153 single-chip transceiver. The on- board clock/data recovery circuitry coverts the AMI/HDB3 ...
Page 7
Functional Description The analog AMI/HDB3 waveform off the E1 line is transformer-coupled into the RRING and RTIP pins of the DS2154. The device recovers clock and data from the analog signal and passes it through the jitter attenuation mux ...
Page 8
Figure 1-1. DS2154 Enhanced E1 Single-Chip Transceiver ...
Page 9
PIN DESCRIPTION PIN NAME 1 RCHBLK 7–10, 15, 23, N.C. 26, 27, 28, 36, 54 8MCLK 6 RCL 11 BTS 12 LIUC 13 8XCLK 14 TEST 16 RTIP 17 RRING 18 RVDD 19, 20, ...
Page 10
PIN NAME 57 D1/AD1 58 D2/AD2 59 D3/AD3 62 D4/AD4 63 D5/AD5 64 D6/AD6 65 D7/AD7 66–72 A0–A6 73 A7/ALE 74 RD(DS WR(R/W) 78 RLINK 79 RLKCLK 82 RCLK 85 RDATA 86 RPOSI 87 RNEGI 88 RCLKI ...
Page 11
Transmit Side Digital Pins PIN NAME Transmit Clock. A 2.048MHz primary clock. Used to clock data through the transmit 46 TCLK side formatter. Must be present for the parallel control port to operate properly. If not present, the Loss ...
Page 12
PIN NAME Transmit Positive Data Input. Sampled on the falling edge of TCLKI for data TPOSI transmitted out onto the E1 line. Can be internally connected to TPOSO by tying the LIUC pin high. Transmit Negative Data ...
Page 13
PIN NAME controlled by the TCR2.0 control bit. This pin can be programmed to either toggle high when the synchronizer is searching for the frame and multiframe or to toggle high if the TCLK pin has not been toggled for ...
Page 14
Line Interface Pins PIN NAME Master Clock Input. A 2.048MHz (±50ppm) clock source with TTL levels is applied at this pin. This clock is used internally for both clock/data recovery and for jitter 21 MCLK attenuation. A quartz crystal ...
Page 15
Table 2-1. Register Map ADDRESS R BPV or Code Violation Count BPV or Code Violation Count CRC4 Error Count 1/FAS Error Count CRC4 Error Count E-Bit ...
Page 16
ADDRESS R/W 2A R/W Transmit Idle Definition 2B R/W Receive Channel Blocking 1 2C R/W Receive Channel Blocking 2 2D R/W Receive Channel Blocking 3 2E R/W Receive Channel Blocking Receive Align Frame 30 R Receive Signaling ...
Page 17
ADDRESS R/W 50 R/W Transmit Si Bits Align Frame 51 R/W Transmit Si Bits Non-Align Frame 52 R/W Transmit Remote Alarm Bits 53 R/W Transmit Sa4 Bits 54 R/W Transmit Sa5 Bits 55 R/W Transmit Sa6 Bits 56 R/W Transmit ...
Page 18
ADDRESS R/W 76 R/W Transmit Channel 23 77 R/W Transmit Channel 24 78 R/W Transmit Channel 25 79 R/W Transmit Channel 26 7A R/W Transmit Channel 27 7B R/W Transmit Channel 28 7C R/W Transmit Channel 29 7D R/W Transmit ...
Page 19
ADDRESS R/W 9C R/W Receive Channel 29 9D R/W Receive Channel 30 9E R/W Receive Channel 31 9F R/W Receive Channel 32 A0 R/W Transmit Channel Control 1 A1 R/W Transmit Channel Control 2 A2 R/W Transmit Channel Control 3 ...
Page 20
PARALLEL PORT The DS2154 is controlled via either a nonmultiplexed (MUX = multiplexed (MUX = 1) bus by an external microcontroller or microprocessor. The DS2154 can operate with either Intel or Motorola bus timing configurations. If ...
Page 21
RCR1: RECEIVE CONTROL REGISTER 1 (Address = 10 Hex) (MSB) RSMF RSM SYMBOL POSITION RSMF RCR1.7 RSM RCR1.6 RSIO RCR1.5 — RCR1.4, RCR1.3 FRC RCR1.2 SYNCE RCR1.1 RESYNC RCR1.0 Table 4-1. Sync/Resync Criteria FRAME OR MULTIFRAME LEVEL FAS present in ...
Page 22
RCR2: RECEIVE CONTROL REGISTER 2 (Address = 11 Hex) (MSB) Sa8S Sa7S SYMBOL POSITION Sa8S RCR2.7 Sa7S RCR2.6 Sa6S RCR2.5 Sa5S RCR2.4 Sa4S RCR2.3 RBCS RCR2.2 RESE RCR2.1 — RCR2.0 Sa6S Sa5S Sa4S NAME AND DESCRIPTION Sa8 Bit Select. Set ...
Page 23
TCR1: TRANSMIT CONTROL REGISTER 1 (Address = 12 Hex) (MSB) ODF TFPT SYMBOL POSITION ODF TCR1.7 TFPT TCR1.6 T16S TCR1.5 TUA1 TCR1.4 TSiS TCR1.3 TSA1 TCR1.2 TSM TCR1.1 TSIO TCR1.0 Note: See Figure 14-11 for more details about how the ...
Page 24
TCR2: TRANSMIT CONTROL REGISTER 2 (Address = 13 Hex) (MSB) Sa8S Sa7S SYMBOL POSITION Sa8S TCR2.7 Sa7S TCR2.6 Sa6S TCR2.5 Sa5S TCR2.4 Sa4S TCR2.3 ODM TCR2.2 AEBE TCR2.1 PF TCR2.0 Sa6S Sa5S Sa4S NAME AND DESCRIPTION Sa8 Bit Select. Set ...
Page 25
CCR1: COMMON CONTROL REGISTER 1 (Address = 14 Hex) (MSB) FLB THDB3 TG802 SYMBOL POSITION FLB CCR1.7 THDB3 CCR1.6 TG802 CCR1.5 TCRC4 CCR1.4 RSM CCR1.3 RHDB3 CCR1.2 RG802 CCR1.1 RCRC4 CCR1.0 TCRC4 RSM RHDB3 NAME AND DESCRIPTION Framer Loopback. 0 ...
Page 26
CCR2: COMMON CONTROL REGISTER 2 (Address = 1A Hex) (MSB) ECUS VCRFS SYMBOL POSITION ECUS CCR2.7 VCRFS CCR2.6 AAIS CCR2.5 ARA CCR2.4 RSERC CCR2.3 LOTCMC CCR2.2 RFF CCR2.1 RFE CCR2.0 AAIS ARA RSERC NAME AND DESCRIPTION Error Counter Update Select. ...
Page 27
CCR3: COMMON CONTROL REGISTER 3 (Address = 1B Hex) (MSB) TESE TCBFS TIRFS SYMBOL POSITION TESE CCR3.7 TCBFS CCR3.6 TIRFS CCR3.5 ESR CCR3.4 RSRE CCR3.3 THSE CCR3.2 TBCS CCR3.1 RCLA CCR3.0 ESR RSRE NAME AND DESCRIPTION Transmit Side Elastic Store ...
Page 28
CCR4: COMMON CONTROL REGISTER 4 (Address = A8 Hex) (MSB) RLB LLB SYMBOL POSITION RLB CCR4.7 LLB CCR4.6 LIAIS CCR4.5 TCM4 CCR4.4 TCM3 CCR4.3 TCM2 CCR4.2 TCM1 CCR4.1 TCM0 CCR4.0 LIAIS TCM4 TCM3 NAME AND DESCRIPTION Remote Loopback ...
Page 29
CCR5: COMMON CONTROL REGISTER 5 (Address = AA Hex) (MSB) LIRST — SYMBOL POSITION LIRST CCR5.7 — CCR5.6, CCR5.5 RCM4 CCR5.4 RCM3 CCR5.3 RCM2 CCR5.2 RCM1 CCR5.1 RCM0 CCR5.0 4.1 Framer Loopback When CCR1.7 is set to 1, the DS2154 ...
Page 30
Power-Up Sequence On power-up, after the supplies are stable, the DS2154 should be configured for operation by writing to all of the internal registers (this includes the Test Registers) since the contents of the internal registers cannot be predicted ...
Page 31
STATUS AND INFORMATION REGISTERS There is a set of four registers that contain information on the current real-time status of the DS2154: Status Register 1 (SR1), Status Register 2 (SR2), Receive Information Register (RIR), and Synchronizer Status Register (SSR). ...
Page 32
RIR: RECEIVE INFORMATION REGISTER (Address = 08 Hex) (MSB) TESF TESE SYMBOL POSITION TESF RIR.7 TESE RIR.6 JALT RIR.5 RESF RIR.4 RESE RIR.3 CRCRC RIR.2 FASRC RIR.1 CASRC RIR.0 JALT RESF RESE NAME AND DESCRIPTION Transmit Side Elastic Store Full. ...
Page 33
SSR: SYNCHRONIZER STATUS REGISTER (Address = 1E Hex) (MSB) CSC5 CSC4 SYMBOL POSITION CSC5 SSR.7 CSC4 SSR.6 CSC3 SSR.5 CSC2 SSR.4 CSC0 SSR.3 FASSA SSR.2 CASSA SSR.1 CRC4SA SSR.0 5.1 CRC4 Sync Counter The CRC4 sync counter increments each time ...
Page 34
SR1: STATUS REGISTER 1 (Address = 06 Hex) (MSB) RSA1 RDMA SYMBOL POSITION RSA1 SR1.7 RDMA SR1.6 RSA0 SR1.5 RSLIP SR1.4 RUA1 SR1.3 RRA SR1.2 RCL SR1.1 RLOS SR1.0 RSA0 RSLIP RUA1 NAME AND DESCRIPTION Receive Signaling All 1s/Signaling Change. ...
Page 35
Table 5-1. Alarm Criteria ALARM RSA1 (receive signaling all 1s) RSA0 (receive signaling all 0s) RDMA (receive distant multiframe alarm) RUA1 (receive unframed all 1s) RRA (receive remote alarm) RCL (receive carrier loss) SET CRITERIA Over 16 consecutive frames (one ...
Page 36
SR2: STATUS REGISTER 2 (Address = 07 Hex) (MSB) RMF RAF SYMBOL POSITION RMF SR2.7 RAF SR2.6 TMF SR2.5 SEC SR2.4 TAF SR2.3 LOTC SR2.2 RCMF SR2.1 TSLIP SR2.0 TMF SEC TAF NAME AND DESCRIPTION Receive CAS Multiframe. Set every ...
Page 37
IMR1: INTERRUPT MASK REGISTER 1 (Address = 16 Hex) (MSB) RSA1 RDMA SYMBOL POSITION RSA1 IMR1.7 RDMA IMR1.6 RSA0 IMR1.5 RSLIP IMR1.4 RUA1 IMR1.3 RRA IMR1.2 RCL IMR1.1 RLOS IMR1.0 RSA0 RSLIP RUA1 NAME AND DESCRIPTION Receive Signaling All 1s/Signaling ...
Page 38
IMR2: INTERRUPT MASK REGISTER 2 (Address = 17 Hex) (MSB) RMF RAF SYMBOL POSITION RMF IMR2.7 RAF IMR2.6 TMF IMR2.5 SEC IMR2.4 TAF IMR2.3 LOTC IMR2.2 RCMF IMR2.1 TSLIP IMR2.0 TMF SEC TAF NAME AND DESCRIPTION Receive CAS Multiframe. 0 ...
Page 39
ERROR COUNT REGISTERS There are a set of four counters in the DS2154 that record bipolar or code violations, errors in the CRC4 SMF codewords, E bits as reported by the far end, and word errors in the FAS. ...
Page 40
CRC4 Error Counter CRC4 Count Register 1 (CRCCR1) is the most significant word and CRCCR2 is the least significant word of a 10-bit counter that records word errors in the Cyclic Redundancy Check 4 (CRC4). Since the maximum CRC4 ...
Page 41
FAS Error Counter FAS Count Register 1 (FASCR1) is the most significant word and FASCR2 is the least significant word of a 12-bit counter that records word errors in the Frame Alignment Signal in time slot 0. This counter ...
Page 42
DS0 MONITORING FUNCTION The DS2154 can monitor one DS0 64kbps channel in the transmit direction and one DS0 channel in the receive direction at the same time. In the transmit direction, the user determines which channel ...
Page 43
CCR5: COMMON CONTROL REGISTER 5 (Address = AA Hex) (Repeated here from Section 4 for convenience.) (MSB) LIRST — SYMBOL POSITION LIRST CCR5.7 — CCR5.6, CCR5.5 RCM4 CCR5.4 RCM3 CCR5.3 RCM2 CCR5.2 RCM1 CCR5.1 RCM0 CCR5.0 — RCM4 RCM3 NAME ...
Page 44
TDS0M: TRANSMIT DS0 MONITOR REGISTER (Address = A9 Hex) (MSB SYMBOL POSITION B1 TDS0M.7 B2 TDS0M.6 B3 TDS0M.5 B4 TDS0M.4 B5 TDS0M.3 B6 TDS0M.2 B7 TDS0M.1 B8 TDS0M NAME AND DESCRIPTION Transmit DS0 Channel Bit ...
Page 45
RDS0M: RECEIVE DS0 MONITOR REGISTER (Address = 1F Hex) (MSB SYMBOL POSITION B1 RDS0M.7 B2 RDS0M.6 B3 RDS0M.5 B4 RDS0M.4 B5 RDS0M.3 B6 RDS0M.2 B7 RDS0M.1 B8 RDS0M NAME AND DESCRIPTION Receive DS0 Channel Bit ...
Page 46
SIGNALING OPERATION The DS2154 contains provisions for both processor-based (i.e., software based) signaling bit access and for hardware-based access. Both the processor-based access and the hardware-based access can be used simultaneously if necessary. The processor-based signaling is covered in ...
Page 47
Each Receive Signaling Register (RS1 to RS16) reports the incoming signaling from two time slots. The bits in the Receive Signaling Registers are updated on multiframe boundaries so the user can use the Receive Multiframe Interrupt in the Receive Status ...
Page 48
Each Transmit Signaling Register (TS1 to TS16) contains the CAS bits for two timeslots that will be inserted into the outgoing stream if enabled via TCR1.5. On multiframe boundaries, the DS2154 will load the values present in ...
Page 49
Hardware-Based Signaling 8.2.1 Receive Side In the receive side of the hardware based signaling, there are two operating modes for the signaling buffer: signaling extraction and signaling reinsertion. Signaling extraction involves pulling the signaling bits from the receive data ...
Page 50
TCBR1/TCBR2/TCBR3/TCBR4: DEFINITION WHEN CCR3 (MSB) CH20 CH4 CH19 CH24 CH8 CH23 CH28 CH12 CH27 CH32 CH16 CH31 * CH1 and CH17 should be set allow the internal TS1 register to create the CAS Multiframe Alignment ...
Page 51
PER-CHANNEL CODE (IDLE) GENERATION AND LOOPBACK The DS2154 can replace data on a channel-by-channel basis in both the transmit and receive directions. The transmit direction is from the backplane to the E1 line and is covered in Section 9.1. ...
Page 52
TIDR: TRANSMIT IDLE DEFINITION REGISTER (Address = 2A Hex) (MSB) TIDR7 TIDR6 TIDR5 SYMBOL POSITION TIDR7 TIDR.7 TIDR0 TIDR.0 9.1.2 Per-Channel Code Insertion The second method involves using the Transmit Channel Control Registers (TCC1/2/3/4) to determine which of the 32 ...
Page 53
Receive Side Code Generation On the receive side, the Receive Channel Control Registers (RCC1/2/3/4) are used to determine which of the 32 E1 channels off the E1 line and going to the backplane should be overwritten with the code ...
Page 54
RCC1/RCC2/RCC3/RCC4: RECEIVE CHANNEL CONTROL REGISTER (Address = Hex) (MSB) CH8 CH7 CH6 CH16 CH15 CH14 CH24 CH23 CH22 CH32 CH31 CH30 SYMBOL POSITION CH1 RCC1.0 CH32 RCC4.7 CH5 CH4 CH3 CH13 CH12 CH11 CH21 CH20 CH19 CH29 ...
Page 55
CLOCK BLOCKING REGISTERS The Receive Channel Blocking Registers (RCBR1/RCBR2/RCBR3/RCBR4) and the Transmit Channel Blocking Registers (TCBR1/TCBR2/TCBR3/TCBR4) control the RCHBLK and TCHBLK pins, respectively. The RCHBLK and TCHCLK pins are user-programmable outputs that can be forced either high or low ...
Page 56
Note: If CCR3 then the TCBRs implies that signaling data sourced from TSER (or TSIG if CCR3 and a 1 implies that signaling data for that channel ...
Page 57
ELASTIC STORES OPERATION The DS2154 contains dual two-frame (512 bits) elastic stores: one for the receive direction and one for the transmit direction. These elastic stores have two main purposes. First, they can be used to rate convert the ...
Page 58
ADDITIONAL (Sa) AND INTERNATIONAL (Si) BIT OPERATION The DS2154 provides for access to both the Sa and the Si bits via three different methods. The first is via a hardware scheme using the RLINK/RLCLK and TLINK/ TLCLK pins. The ...
Page 59
RAF: RECEIVE ALIGN FRAME REGISTER (Address = 2F Hex) (MSB SYMBOL POSITION Si RAF.7 0 RAF.6 0 RAF.5 1 RAF.4 1 RAF.3 0 RAF.2 1 RAF.1 1 RAF.0 RNAF: RECEIVE NON-ALIGN FRAME REGISTER (Address = 1F Hex) (MSB) ...
Page 60
TAF: TRANSMIT ALIGN FRAME REGISTER (Address = 20 Hex) (MSB (Note: Must be programmed with the 7-bit FAS word; the DS2154 does not automatically set these bits.) SYMBOL POSITION Si TAF.7 0 TAF.6 0 TAF.5 1 TAF.4 1 ...
Page 61
Internal Register Scheme Based on CRC4 Multiframe On the receive side, there is a set of eight registers (RSiAF, RSiNAF, RRA, RSa4 to RSa8) that report the Si and Sa bits as they are received. These registers are updated ...
Page 62
TSaCR: TRANSMIT Sa BIT CONTROL REGISTER (Address = 1C Hex) (MSB) SiAF SiNAF SYMBOL POSITION SiAF TSaCR.7 SiNAF TSaCR.6 RA TSaCR.5 Sa4 TSaCR.4 Sa5 TSaCR.3 Sa6 TSaCR.2 Sa7 TSaCR.1 Sa8 TSaCR.0 RA Sa4 Sa5 NAME AND DESCRIPTION International Bit in ...
Page 63
LINE INTERFACE FUNCTION The line interface function in the DS2152 contains three sections: the receiver, which handles clock and data recovery; the transmitter, which waveshapes and drives the E1 line; and the jitter attenuator. Each of these three sections ...
Page 64
Receive Clock and Data Recovery The DS2154 contains a digital clock recovery system. See The DS2154 couples to the receive E1 shielded twisted pair or coax via a 1:1 transformer. See for transformer details. The 2.048MHz clock attached at ...
Page 65
Table 13-2. The line driver in the DS2154 contains a current limiter that prevents more than 50mA (RMS) from being sourced in a 1Ω load. Table 13-2. Transformer Specifications SPECIFICATION Turns Ratio Primary Inductance Leakage Inductance Intertwining Capacitance DC ...
Page 66
Figure 13-1. External Analog Connections NOTE 1: RESISTOR VALUES ARE ±1%. NOTE 2: THE R RESISTORS ARE USED TO INCREASE THE TRANSMITTER RETURN LOSS OR TO PROTECT THE DEVICE FROM OVERVOLTAGE. T NOTE 3: THE R RESISTORS ARE USED TO ...
Page 67
Figure 13-2. Jitter Tolerance Figure 13-3. Transmit Waveform Template ...
Page 68
Figure 13-4. Jitter Attenuation ...
Page 69
TIMING DIAGRAMS Figure 14-1. Receive Side Timing NOTE 1: RSYNC IN THE FRAME MODE (RCR1.6 = 0). NOTE 2: RSYNC IN THE FRAME MODE (RCR1.6 = 0). NOTE 3: RSYNC IS PROGRAMMED TO PULSE HIGH DURING THE Sa4 BIT ...
Page 70
Figure 14-3. Receive Side 1.544MHz Boundary Timing (with Elastic Store Enabled) NOTE 1: DATA FROM THE E1 CHANNELS 13, 17, 21, 25, AND 29 IS DROPPED (CHANNEL 2 FROM THE E1 LINK IS MAPPED TO CHANNEL 1 ...
Page 71
Figure 14-5. Transmit Side Timing NOTE 1: TSYNC IN THE FRAME MODE (TCR1.1 = 0). NOTE 2: TSYNC IN THE MULTIFRAME MODE (TCR1.1 = 1). NOTE 4: TLINK IS PROGRAMMED TO SOURCE ONLY THE Sa4 BIT. NOTE 5: THIS DIAGRAM ...
Page 72
Figure 14-7. Transmit Side 1.544MHz Boundary Timing (with Elastic Store Enabled) NOTE 1: TCHBLK IS PROGRAMMED TO BLOCK CHANNEL 24. NOTE 2: THE F-BIT POSITION IS IGNORED BY THE DS2154. Figure 14-8. Transmit Side 2.048MHz Boundary Timing (with Elastic Store ...
Page 73
Figure 14-9. G.802 Timing NOTE 1: RCHBLK OR TCHBLK IS PROGRAMMED TO PULSE HIGH DURING TIME SLOTS 1 TO 15, 17, 25, AND DURING BIT 1 OF TIME SLOT 26 ...
Page 74
Figure 14-10. Synchronization Flow Chart ...
Page 75
Figure 14-11. Transmit Data Flow NOTE 1: TCLK SHOULD BE TIED TO RCLK AND TSYNC SHOULD BE TIED TO RFSYNC FOR DATA TO BE PROPERLY SOURCED FROM RSER. NOTE 2: AUTO REMOTE ALARM IF ENABLED WILL ONLY OVERWRITE BIT 3 ...
Page 76
DC CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground……………………………………………..-1.0V to +7.0V Operating Temperature Range Commercial……………………………………………………………………………0°C to +70°C Industrial…………………………………………………………………………….-40°C to +85°C Storage Temperature……………………………………………………………………….-55°C to +125°C Soldering Temperature……………………………………………See IPC/JEDEC STD-020 Specification This is a stress rating only ...
Page 77
AC CHARACTERISTICS Table 16-1. AC Characteristics—Multiplexed Parallel Port (MUX = ± 0°C to +70°C for DS2154L (See Figure 16-1, Figure 16-2, and PARAMETER Cycle Time Pulse Width, DS ...
Page 78
Figure 16-2. Intel Bus Write AC Timing (BTS = 0/MUX = 1) Figure 16-3. Motorola Bus AC Timing (BTS = 1/MUX = ...
Page 79
Table 16-2. AC Characteristics—Receive Side = 5V ± 0°C to +70°C for DS2154L (See Figure 16-4, Figure 16-5, and PARAMETER RCLKO Period RCLKO Pulse Width RCLKO Pulse Width RCLKI Period RCLKI Pulse ...
Page 80
Figure 16-4. Receive Side AC Timing NOTE 1: RSYNC IS IN THE OUTPUT MODE (RCR1.5 = 0). NOTE 2: RLCLK ONLY PULSES HIGH DURING Sa BIT LOCATIONS AS DEFINTED IN RCR2; NO RELATIONSHIP BETWEEN RLCLK AND RSYNC OR RFSYNC IS ...
Page 81
Figure 16-5. Receive System Side AC Timing NOTE 1: RSYNC IS IN THE OUTPUT MODE (RCR1.5 = 0). NOTE 2: RSYNC IS IN THE INPUT MODE (RCR1.5 = 1). Figure 16-6. Receive Line Interface AC Timing ...
Page 82
Table 16-3. AC Characteristics—Transmit Side = 5V ± 0°C to +70°C for DS2154L (See Figure 16-7, Figure 16-8, and PARAMETER TCLK Period TCLK Pulse Width TCLKI Period TCLKI Pulse Width TSYSCLK Period ...
Page 83
Figure 16-7. Transmit Side AC Timing NOTE 1: TSYNC IS IN THE OUTPUT MODE (TCR1.0 = 1). NOTE 2: TSYNC IS IN THE INPUT MODE (TCR1.0 = 0). NOTE 3: TSER IS SAMPLED ON THE FALLING EDGE OF TCLK WHEN ...
Page 84
Figure 16-8. Transmit System Side AC Timing NOTE 1: TSER IS ONLY SAMPLED ON THE FALLING EDGE OF TSYSCLK WHEN THE TRANSMIT SIDE ELASTIC STORE IS ENABLED. NOTE 2: TCHCLK AND TCHBLK ARE SYNCHRONOUS WITH TSYSCLK WHEN THE TRANSMIT SIDE ...
Page 85
Table 16-4. AC Characteristics—Nonmultiplexed Parallel Port (MUX = ± 0°C to +70°C for DS2154L (See Figure 16-10, Figure 16-11, PARAMETER Setup Time for Valid to Active ...
Page 86
Figure 16-11. Intel Bus Write AC Timing (BTS=0/MUX=0) Figure 16-12. Motorola Bus Read AC Timing (BTS = 1/MUX = 0) Figure 16-13. Motorola Bus Write AC Timing (BTS = 1/MUX = ...
Page 87
... No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor © 2006 Maxim Integrated Products • Printed USA ...