DS33R41+ Maxim Integrated Products, DS33R41+ Datasheet - Page 204

• Manufacturer Part Number: DS33R41+
• Description: IC TXRX ETHERNET MAP 400-BGA
• Manufacturer: Maxim Integrated Products
• Type: Transceiverr

Specifications of DS33R41+

• Number Of Drivers/receivers: 4/4
• Protocol: T1/E1/J1
• Voltage - Supply: 3.14 V ~ 3.47 V
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 7 to 4: Device ID (ID7 to ID4). The upper four bits of TR.IDR are used to display the transceiver ID.
Bits 3 to 0: Chip Revision Bits (ID3 to ID0). The lower four bits of TR.IDR are used to display the die revision of
the chip. IDO is the LSB of a decimal code that represents the chip revision.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: Receive Pulse-Density Violation Event (RPDV). Set when the receive data stream does not meet the
ANSI T1.403 requirements for pulse density.
Bit 6: Transmit Pulse-Density Violation Event (TPDV). Set when the transmit data stream does not meet the
ANSI T1.403 requirements for pulse density.
Bit 5: Change-of-Frame Alignment Event (COFA). Set when the last resync resulted in a change-of-frame or
multiframe alignment.
Bit 4: Eight Zero-Detect Event (8ZD). Set when a string of at least eight consecutive 0s (regardless of the length
of the string) have been received at RPOSI and RNEGI.
Bit 3: Sixteen Zero-Detect Event (16ZD). Set when a string of at least 16 consecutive 0s (regardless of the length
of the string) have been received at RPOSI and RNEGI.
Bit 2: Severely Errored Framing Event (SEFE). Set when two out of six framing bits (Ft or FPS) are received in
error.
Bit 1: B8ZS Codeword Detect Event (B8ZS). Set when a B8ZS codeword is detected at RPOS and RNEG
independent of whether the B8ZS mode is selected or not by TR.T1TCR2.7. Useful for automatically setting the
line coding.
Bit 0: Frame Bit-Error Event (FBE). Set when an Ft (D4) or FPS (ESF) framing bit is received in error.
RPDV
ID7
1
7
7
0
TR.IDR
Device Identification Register
0Fh
TR.INFO1
Information Register 1
10h
TPDV
ID6
6
6
0
0
COFA
ID5
5
0
5
0
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8ZD
ID4
4
0
4
0
16ZD
ID3
X
3
3
0
SEFE
ID2
X
2
2
0
B8ZS
ID1
X
1
1
0
FBE
ID0
X
0
0
0