PIC17C756A-33/L Microchip Technology Inc., PIC17C756A-33/L Datasheet - Page 170

• Manufacturer Part Number: PIC17C756A-33/L
• Description: 68 PIN, 32 KB OTP, 902 RAM, 50 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC17C756A-33/L

• A/d Inputs: 12-Channel, 10-Bit
• Cpu Speed: 8.25 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 52
• Interface: I2C/SPI/USART
• Memory Type: OTP
• Number Of Bits: 8
• Package Type: 68-pin PLCC
• Programmable Memory: 32K Bytes
• Ram Size: 902 Bytes
• Speed: 16 MHz
• Timers: 2-8-bit, 2-16-bit
• Voltage, Range: 3-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

PIC17C7XX
15.2.18
Multi-Master mode support is achieved by bus arbitra-
tion. When the master outputs address/data bits onto
the SDA pin, arbitration takes place when the master
outputs a ’1’ on SDA, by letting SDA float high and
another master asserts a ’0’. When the SCL pin floats
high, data should be stable. If the expected data on
SDA is a ’1’ and the data sampled on the SDA pin = ’0’,
then a bus collision has taken place. The master will
set the Bus Collision Interrupt Flag, BCLIF and reset
the I
If a transmit was in progress when the bus collision
occurred, the transmission is halted, the BF flag is
cleared, the SDA and SCL lines are de-asserted and
the SSPBUF can be written to. When the user ser-
vices the bus collision Interrupt Service Routine and if
the I
tion by asserting a START condition.
FIGURE 15-34:
DS30289B-page 170
SDA
SCL
BCLIF
2
2
C port to its IDLE state (Figure 15-34).
C bus is free, the user can resume communica-
MULTI -MASTER COMMUNICATION,
BUS COLLISION AND BUS
ARBITRATION
BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE
Data changes
while SCL = 0.
SDA released
by master.
SDA line pulled low
by another source.
If a START, Repeated Start, STOP, or Acknowledge
condition was in progress when the bus collision
occurred, the condition is aborted, the SDA and SCL
lines are de-asserted and the respective control bits in
the SSPCON2 register are cleared. When the user
services the bus collision Interrupt Service Routine,
and if the I
nication by asserting a START condition.
The master will continue to monitor the SDA and SCL
pins and if a STOP condition occurs, the SSPIF bit will
be set.
A write to the SSPBUF will start the transmission of
data at the first data bit, regardless of where the trans-
mitter left off when bus collision occurred.
In Multi-Master mode, the interrupt generation on the
detection of START and STOP conditions allows the
determination of when the bus is free. Control of the
I
STAT register, or the bus is idle and the S and P bits
are cleared.
2
C bus can be taken when the P bit is set in the SSP-
2
C bus is free, the user can resume commu-
Sample SDA. While SCL is high
data doesn’t match what is driven
by the master.
Bus collision has occurred.
Set bus collision
interrupt.
2000 Microchip Technology Inc.