PIC17C756A-33/L Microchip Technology Inc., PIC17C756A-33/L Datasheet - Page 56

• Manufacturer Part Number: PIC17C756A-33/L
• Description: 68 PIN, 32 KB OTP, 902 RAM, 50 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC17C756A-33/L

• A/d Inputs: 12-Channel, 10-Bit
• Cpu Speed: 8.25 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 52
• Interface: I2C/SPI/USART
• Memory Type: OTP
• Number Of Bits: 8
• Package Type: 68-pin PLCC
• Programmable Memory: 32K Bytes
• Ram Size: 902 Bytes
• Speed: 16 MHz
• Timers: 2-8-bit, 2-16-bit
• Voltage, Range: 3-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

PIC17C7XX
7.7
The Program Counter (PC) is a 16-bit register. PCL, the
low byte of the PC, is mapped in the data memory. PCL
is readable and writable just as is any other register.
PCH is the high byte of the PC and is not directly
addressable. Since PCH is not mapped in data or pro-
gram memory, an 8-bit register PCLATH (PC high
latch) is used as a holding latch for the high byte of the
PC. PCLATH is mapped into data memory. The user
can read or write PCH through PCLATH.
The 16-bit wide PC is incremented after each instruc-
tion fetch during Q1 unless:
• Modified by a GOTO, CALL, LCALL, RETURN,
• Modified by an interrupt response
• Due to destination write to PCL by an instruction
“Skips” are equivalent to a forced NOP cycle at the
skipped address.
Figure 7-7 and Figure 7-8 show the operation of the
program counter for various situations.
FIGURE 7-7:
FIGURE 7-8:
DS30289B-page 56
RETLW, or RETFIE instruction
PC<15:13>
15
15
7
Program Counter Module
3
5 4
13
PCH
PCLATH
8
Internal Data Bus <8>
12
PCLATH
PCH
From Instruction
5
PROGRAM COUNTER
OPERATION
PROGRAM COUNTER
USING THE CALL AND
GOTO INSTRUCTIONS
8
8
8 7
8 7
0
PCL
8
PCL
8
0
0
Using Figure 7-7, the operations of the PC and
PCLATH for different instructions are as follows:
a)
b)
c)
d)
e)
Using Figure 7-8, the operation of the PC and PCLATH
for GOTO and CALL instructions is as follows:
The read-modify-write only affects the PCL with the
result. PCH is loaded with the value in the PCLATH. For
example, ADDWF PCL will result in a jump within the
current page. If PC = 03F0h, WREG = 30h and
PCLATH = 03h before instruction, PC = 0320h after the
instruction. To accomplish a true 16-bit computed jump,
the user needs to compute the 16-bit destination
address, write the high byte to PCLATH and then write
the low value to PCL.
The following PC related operations do not change
PCLATH:
a)
b)
c)
LCALL instructions:
An 8-bit destination address is provided in the
instruction (opcode). PCLATH is unchanged.
PCLATH
Opcode<7:0>
Read instructions on PCL:
Any instruction that reads PCL.
PCL
PCH
Write instructions on PCL:
Any instruction that writes to PCL.
8-bit data
PCLATH
Read-Modify-Write instructions on PCL:
Any instruction that does a read-write-modify
operation on PCL, such as ADDWF PCL.
Read:
Write:
RETURN instruction:
Stack<MRU>
CALL, GOTO instructions:
A 13-bit destination address is provided in the
instruction (opcode).
Opcode<12:0>
PC<15:13>
Opcode<12:8>
LCALL, RETLW, and RETFIE instructions.
Interrupt vector is forced onto the PC.
Read-modify-write instructions on PCL
(e.g. BSF PCL).
data bus
PCLATH
PCL
8-bit result
PCLATH
PCH
PCH
data bus
PCLATH<7:5>
PC<15:0>
PCL
data bus
PC<12:0>
PCLATH<4:0>
ALU or destination
2000 Microchip Technology Inc.
PCH
data bus
PCL
ALU
PCL