PIC17C756A-33/L Microchip Technology Inc., PIC17C756A-33/L Datasheet - Page 38

• Manufacturer Part Number: PIC17C756A-33/L
• Description: 68 PIN, 32 KB OTP, 902 RAM, 50 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC17C756A-33/L

• A/d Inputs: 12-Channel, 10-Bit
• Cpu Speed: 8.25 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 52
• Interface: I2C/SPI/USART
• Memory Type: OTP
• Number Of Bits: 8
• Package Type: 68-pin PLCC
• Programmable Memory: 32K Bytes
• Ram Size: 902 Bytes
• Speed: 16 MHz
• Timers: 2-8-bit, 2-16-bit
• Voltage, Range: 3-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

PIC17C7XX
REGISTER 6-5: PIR2 REGISTER (ADDRESS: 10h, BANK 4)
DS30289B-page 38
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Legend:
R = Readable bit
- n = Value at POR Reset
bit 7
SSPIF: Synchronous Serial Port (SSP) Interrupt Flag bit
1 = The SSP interrupt condition has occurred and must be cleared in software before returning
0 = An SSP interrupt condition has NOT occurred
BCLIF: Bus Collision Interrupt Flag bit
1 = A bus collision has occurred in the SSP, when configured for I
0 = No bus collision has occurred
ADIF: A/D Module Interrupt Flag bit
1 = An A/D conversion is complete
0 = An A/D conversion is not complete
Unimplemented: Read as ’0’
CA4IF: Capture4 Interrupt Flag bit
1 = Capture event occurred on RE3/CAP4 pin
0 = Capture event did not occur on RE3/CAP4 pin
CA3IF: Capture3 Interrupt Flag bit
1 = Capture event occurred on RG4/CAP3 pin
0 = Capture event did not occur on RG4/CAP3 pin
TX2IF:USART2 Transmit Interrupt Flag bit (state controlled by hardware)
1 = USART2 Transmit buffer is empty
0 = USART2 Transmit buffer is full
RC2IF: USART2 Receive Interrupt Flag bit (state controlled by hardware)
1 = USART2 Receive buffer is full
0 = USART2 Receive buffer is empty
SSPIF
R/W-0
from the Interrupt Service Routine. The conditions that will set this bit are:
SPI:
A transmission/reception has taken place.
I
A transmission/reception has taken place.
I
The initiated START condition was completed by the SSP module.
The initiated STOP condition was completed by the SSP module.
The initiated Restart condition was completed by the SSP module.
The initiated Acknowledge condition was completed by the SSP module.
A START condition occurred while the SSP module was idle (Multi-master system).
A STOP condition occurred while the SSP module was idle (Multi-master system).
2
2
C Slave/Master:
C Master:
R/W-0
BCLIF
R/W-0
ADIF
W = Writable bit
’1’ = Bit is set
U-0
—
CA4IF
R/W-0
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
R/W-0
CA3IF
2
C Master mode
2000 Microchip Technology Inc.
x = Bit is unknown
TX2IF
R-1
RC2IF
R-0
bit 0