PIC16F676-I/ST Microchip Technology Inc., PIC16F676-I/ST Datasheet - Page 44

• Manufacturer Part Number: PIC16F676-I/ST
• Description: 14 PIN, 1.75 KB FLASH, 64 RAM, 12 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F676-I/ST

• Comparators: 1
• Cpu Speed: 5 MIPS
• Eeprom Memory: 128 Bytes
• Input Output: 12
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 14-pin TSSO
• Programmable Memory: 1.75K Bytes
• Ram Size: 64 Bytes
• Speed: 20 MHz
• Timers: 1-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F630/676
REGISTER 6-2:
6.9
The comparator interrupt flag is set whenever there is
a change in the output value of the comparator.
Software will need to maintain information about the
status of the output bits, as read from CMCON<6>, to
determine the actual change that has occurred. The
CMIF bit, PIR1<3>, is the comparator interrupt flag.
This bit must be reset in software by clearing it to ‘0’.
Since it is also possible to write a '1' to this register, a
simulated interrupt may be initiated.
The
(INTCON<6>) must be set to enable the interrupt. In
addition, the GIE bit must also be set. If any of these
bits are cleared, the interrupt is not enabled, though the
CMIF bit will still be set if an interrupt condition occurs.
TABLE 6-2:
DS40039C-page 42
0Bh/8Bh
0Ch
19h
8Ch
85h
99h
Legend:
Address
CMIE
Comparator Interrupts
bit 7
bit 6
bit 5
bit 4
bit 3-0
INTCON
PIR1
CMCON
PIE1
TRISA
VRCON
Name
x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the comparator module.
bit
REGISTERS ASSOCIATED WITH COMPARATOR MODULE
(PIE1<3>)
VREN
VRCON — VOLTAGE REFERENCE CONTROL REGISTER (ADDRESS: 99h)
Bit 7
EEIF
EEIE
bit 7
GIE
VREN: CV
1 = CV
0 = CV
Unimplemented: Read as '0'
VRR: CV
1 = Low range
0 = High range
Unimplemented: Read as '0'
VR3:VR0: CV
When VRR = 1: CV
When VRR = 0: CV
Legend:
R = Readable bit
- n = Value at POR
—
—
R/W-0
VREN
REF
REF
COUT
ADIF
ADIE
Bit 6
PEIE
and
REF
—
—
REF
circuit powered on
circuit powered down, no I
Range Selection bit
REF
Enable bit
U-0
the
—
TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111
Bit 5
T0IE
VRR
value selection 0 ≤ VR [3:0] ≤ 15
—
—
—
REF
REF
PEIE
= (VR3:VR0 / 24) * V
= V
R/W-0
INTE
CINV
Bit 4
VRR
DD
—
—
—
W = Writable bit
’1’ = Bit is set
bit
/4 + (VR3:VR0 / 32) * V
CMIE
RAIE
CMIF
Bit 3
VR3
CIS
R/W-0
DD
—
The user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a)
b)
A mismatch condition will continue to set flag bit CMIF.
Reading CMCON will end the mismatch condition and
allow flag bit CMIF to be cleared.
drain
Note:
Any read or write of CMCON. This will end the
mismatch condition.
Clear flag bit CMIF.
Bit 2
CM2
DD
T0IF
VR2
—
—
R/W-0
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
VR3
If a change in the CMCON register (COUT)
should occur when a read operation is
being executed (start of the Q2 cycle), then
the CMIF (PIR1<3>) interrupt flag may not
get set.
DD
Bit 1
INTF
CM1
VR1
—
—
TMR1IF 00-- 0--0 00-- 0--0
TMR1IE 00-- 0--0 00-- 0--0
R/W-0
VR2
RAIF
Bit 0
CM0
VR0
 2003 Microchip Technology Inc.
0000 0000 0000 000u
-0-0 0000 -0-0 0000
0-0- 0000 0-0- 0000
POR, BOD
Value on
x = Bit is unknown
R/W-0
VR1
Value on
RESETS
all other
R/W-0
VR0
bit 0