PIC16F676-I/ST Microchip Technology Inc., PIC16F676-I/ST Datasheet - Page 50

• Manufacturer Part Number: PIC16F676-I/ST
• Description: 14 PIN, 1.75 KB FLASH, 64 RAM, 12 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F676-I/ST

• Comparators: 1
• Cpu Speed: 5 MIPS
• Eeprom Memory: 128 Bytes
• Input Output: 12
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 14-pin TSSO
• Programmable Memory: 1.75K Bytes
• Ram Size: 64 Bytes
• Speed: 20 MHz
• Timers: 1-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F630/676
7.3
The A/D converter module can operate during SLEEP.
This requires the A/D clock source to be set to the
internal oscillator. When the RC clock source is
selected, the A/D waits one instruction before starting
the conversion. This allows the SLEEP instruction to be
executed, thus eliminating much of the switching noise
from the conversion. When the conversion is complete,
the GO/DONE bit is cleared, and the result is loaded
into the ADRESH:ADRESL registers. If the A/D
interrupt is enabled, the device awakens from SLEEP.
If the A/D interrupt is not enabled, the A/D module is
turned off, although the ADON bit remains set.
TABLE 7-2:
DS40039C-page 48
Address
05h
07h
0Bh, 8Bh INTCON
0Ch
1Eh
1Fh
85h
87h
8Ch
91h
9Eh
9Fh
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used for A/D converter module.
A/D Operation During SLEEP
ADRESH Most Significant 8 bits of the Left Shifted A/D result or 2 bits of the Right Shifted Result
ADCON0
ADRESL Least Significant 2 bits of the Left Shifted A/D Result or 8 bits of the Right Shifted Result
ADCON1
PORTA
PORTC
PIR1
TRISA
TRISC
PIE1
ANSEL
Name
SUMMARY OF A/D REGISTERS
ADFM
ANS7
EEIF
EEIE
Bit 7
GIE
—
—
—
—
—
ADCS2
VCFG
ANS6
PEIE
ADIF
ADIE
Bit 6
—
—
—
—
PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 --xx xxxx --uu uuuu
PORTA5 PORTA4 PORTA3 PORTA2 PORTA1 PORTA0 --xx xxxx --uu uuuu
TRISA5
TRISC5
ADCS1
ANS5
Bit 5
T0IE
—
—
—
TRISC4
TRISA4
ADCS0
CHS2
ANS4
INTE
Bit 4
—
—
TRISA3
TRISC3
CHS1
ANS3
CMIF
CMIE
RAIE
Bit 3
—
When the A/D clock source is something other than
RC, a SLEEP instruction causes the present conversion
to be aborted, and the A/D module is turned off. The
ADON bit remains set.
7.4
A device RESET forces all registers to their RESET
state. Thus, the A/D module is turned off and any
pending conversion is aborted. The ADRESH:ADRESL
registers are unchanged.
TRISC2
TRISA2
CHS0
ANS2
Bit 2
T0IF
—
—
—
Effects of RESET
TRISC1
TRISA1
ANS1
Bit 1
INTF
GO
—
—
—
 2003 Microchip Technology Inc.
TMR1IF 00-- 0--0 00-- 0--0
TRISC0 --11 1111 --11 1111
TMR1IE 00-- 0--0 00-- 0--0
TRISA0 --11 1111 --11 1111
ADON
ANS0
Bit 0
RAIF
—
0000 0000 0000 000u
xxxx xxxx uuuu uuuu
00-0 0000 00-0 0000
1111 1111 1111 1111
xxxx xxxx uuuu uuuu
-000 ---- -000 ----
POR, BOD
Value on:
Value on
RESETS
all other