PIC24FJ256GB210-I/PT Microchip Technology Inc., PIC24FJ256GB210-I/PT Datasheet - Page 207

• Manufacturer Part Number: PIC24FJ256GB210-I/PT
• Description: 100 TQFP 12x12x1mm TRAY, 16-bit, 256KB Flash, 96K RAM, USB
• Manufacturer: Microchip Technology Inc.

Specifications of PIC24FJ256GB210-I/PT

• A/d Inputs: 24 Channel, 10-bit
• Comparators: 3
• Cpu Speed: 16 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 84
• Interface: I2C/SPI/UART/USART/USB
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 100-pin TQFP
• Programmable Memory: 256K Bytes
• Ram Size: 98K Bytes
• Speed: 32 MHz
• Temperature Range: –40 to 85 °C
• Timers: 5-16-bit
• Voltage, Range: 2.2-3.6 V
• Lead Free Status / Rohs Status: RoHS Compliant part

To set up the SPI module for the Enhanced Buffer
Master mode of operation:
1.
2.
3.
4.
5.
6.
FIGURE 15-2:
 2010 Microchip Technology Inc.
If using interrupts:
a)
b)
c)
Write the desired settings to the SPIxCON1
and
(SPIxCON1<5>) = 1.
Clear the SPIROV bit (SPIxSTAT<6>).
Select Enhanced Buffer mode by setting the
SPIBEN bit (SPIxCON2<0>).
Enable SPI operation by setting the SPIEN bit
(SPIxSTAT<15>).
Write the data to be transmitted to the SPIxBUF
register. Transmission (and reception) will start
as soon as data is written to the SPIxBUF
register.
SSx/FSYNCx
SDOx
SCKx
SDIx
Clear the SPIxIF bit in the respective IFS
register.
Set the SPIxIE bit in the respective IEC
register.
Write the SPIxIP bits in the respective IPC
register.
SPIxCON2
Read SPIxBUF
Control
Transfer
Sync
SPIx MODULE BLOCK DIAGRAM (ENHANCED MODE)
registers
Receive Buffer
8-Level FIFO
bit 0
SPIxSR
with
Control
SPIXBUF
Clock
Transmit Buffer
Shift Control
8-Level FIFO
MSTEN
PIC24FJ256GB210 FAMILY
Transfer
Write SPIxBUF
Select
Edge
To set up the SPI module for the Enhanced Buffer
Slave mode of operation:
1.
2.
3.
4.
5.
6.
7.
8.
16
Clear the SPIxBUF register.
If using interrupts:
a)
b)
c)
Write the desired settings to the SPIxCON1
and
(SPIxCON1<5>) = 0.
Clear the SMP bit.
If the CKE bit is set, then the SSEN bit must be
set, thus enabling the SSx pin.
Clear the SPIROV bit (SPIxSTAT<6>).
Select Enhanced Buffer mode by setting the
SPIBEN bit (SPIxCON2<0>).
Enable SPI operation by setting the SPIEN bit
(SPIxSTAT<15>).
Clear the SPIxIF bit in the respective IFS
register.
Set the SPIxIE bit in the respective IEC
register.
Write the SPIxIP bits in the respective IPC
register to set the interrupt priority.
Secondary
1:1 to 1:8
Prescaler
SPIxCON2
Internal Data Bus
1:1/4/16/64
registers
Prescaler
Primary
DS39975A-page 207
SPIxCON1<1:0>
SPIxCON1<4:2>
Enable
Master Clock
with
F
CY
MSTEN