PIC24FJ256GB210-I/PT Microchip Technology Inc., PIC24FJ256GB210-I/PT Datasheet - Page 23

• Manufacturer Part Number: PIC24FJ256GB210-I/PT
• Description: 100 TQFP 12x12x1mm TRAY, 16-bit, 256KB Flash, 96K RAM, USB
• Manufacturer: Microchip Technology Inc.

Specifications of PIC24FJ256GB210-I/PT

• A/d Inputs: 24 Channel, 10-bit
• Comparators: 3
• Cpu Speed: 16 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 84
• Interface: I2C/SPI/UART/USART/USB
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 100-pin TQFP
• Programmable Memory: 256K Bytes
• Ram Size: 98K Bytes
• Speed: 32 MHz
• Temperature Range: –40 to 85 °C
• Timers: 5-16-bit
• Voltage, Range: 2.2-3.6 V
• Lead Free Status / Rohs Status: RoHS Compliant part

TABLE 1-3:
 2010 Microchip Technology Inc.
CN81
CN82
CN83
CN84
CTEDG1
CTEDG2
CTPLS
CV
D+
D-
DMH
DMLN
DPH
DPLN
ENVREG
INT0
MCLR
OSCI
OSCO
PGEC1
PGED1
PGEC2
PGED2
PGEC3
PGED3
Legend:
Note 1:
Function
REF
2:
3:
4:
TTL = TTL input buffer
ANA = Analog level input/output
The alternate EPMP pins are selected when the ALTPMP (CW3<12>) bit is programmed to ‘0’.
The PMSC2 signal will replace the PMA15 signal on the 15-pin PMA when CSF<1:0> = 01 or 10.
The PMCS1 signal will replace the PMA14 signal on the 14-pin PMA when CSF<1:0> = 10.
The alternate V
TQFP/QFN
64-Pin
37
36
28
27
29
23
37
36
46
42
50
43
57
46
39
40
15
16
17
18
12
—
—
11
7
PIC24FJ256GB210 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin Number
REF
100-Pin
TQFP
pins selected when the ALTVREF (CW1<5>) bit is programmed to ‘0’.
95
57
56
42
41
43
34
57
56
72
68
77
69
86
72
13
63
64
24
25
26
27
20
21
1
121-Pin
BGA
H10
H10
A10
E10
F11
J11
J11
C4
B2
K7
D9
E9
D9
F1
F9
K1
K2
H1
H2
L7
J7
L5
J7
L1
J3
PIC24FJ256GB210 FAMILY
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
Buffer
Input
ANA
ANA
ANA
ANA
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
—
—
—
—
—
—
—
—
ST = Schmitt Trigger input buffer
I
2
C™ = I
Interrupt-on-Change Inputs.
CTMU External Edge Input 1.
CTMU External Edge Input 2.
CTMU Pulse Output.
Comparator Voltage Reference Output.
USB Differential Plus Line (internal transceiver).
USB Differential Minus Line (internal transceiver).
D- External Pull-up Control Output.
D- External Pull-down Control Output.
D+ External Pull-up Control Output.
D+ External Pull-down Control Output.
Voltage Regulator Enable.
External Interrupt Input.
Master Clear (device Reset) Input. This line is brought low
to cause a Reset.
Main Oscillator Input Connection.
Main Oscillator Output Connection.
In-Circuit Debugger/Emulator/ICSP™ Programming Clock 1.
In-Circuit Debugger/Emulator/ICSP Programming Data 1.
In-Circuit Debugger/Emulator/ICSP Programming Clock 2.
In-Circuit Debugger/Emulator/ICSP Programming Data 2.
In-Circuit Debugger/Emulator/ICSP Programming Clock 3.
In-Circuit Debugger/Emulator/ICSP Programming Data 3.
2
C/SMBus input buffer
Description
DS39975A-page 23