PIC18F6680-I/PT Microchip Technology Inc., PIC18F6680-I/PT Datasheet - Page 273

• Manufacturer Part Number: PIC18F6680-I/PT
• Description: 64 PIN, 64 KB FLASH, 3328 RAM, 52 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F6680-I/PT

• A/d Inputs: 12-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1024 Bytes
• Input Output: 53
• Interface: CAN/I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 64-pin TQFP
• Programmable Memory: 64K Bytes
• Ram Size: 3.3K Bytes
• Speed: 40 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

TABLE 24-3:
24.4.1
The user memory may be read to or written from any
location using the table read and table write instruc-
tions. The Device ID register may be read with table
reads. The Configuration registers may be read and
written with the table read and table write instructions.
In user mode, the CPn bits have no direct effect. CPn
bits inhibit external reads and writes. A block of user
memory may be protected from table writes if the
WRTn configuration bit is ‘0’. The EBTRn bits control
table reads. For a block of user memory with the
EBTRn bit set to ‘0’, a table read instruction that
executes from within that block is allowed to read. A
 2005 Microchip Technology Inc.
300008h
300009h
30000Ah
30000Bh
30000Ch
30000Dh
Legend: Shaded cells are unimplemented.
Note 1:
File Name
Unimplemented in PIC18FX525 devices.
PROGRAM MEMORY
CODE PROTECTION
CONFIG5L
CONFIG5H
CONFIG6L
CONFIG6H
CONFIG7L
CONFIG7H
SUMMARY OF REGISTERS ASSOCIATED WITH CODE PROTECTION
WRTD
Bit 7
CPD
—
—
—
—
EBTRB
WRTB
Bit 6
CPB
—
—
—
PIC18F6525/6621/8525/8621
WRTC
Bit 5
—
—
—
—
—
table read instruction that executes from a location out-
side of that block is not allowed to read and will result
in reading ‘0’s. Figures 24-4 through 24-6 illustrate
table write and table read protection.
Bit 4
—
—
—
—
—
—
Note:
EBTR3
WRT3
Code protection bits may only be written to
a ‘0’ from a ‘1’ state. It is not possible to
write a ‘1’ to a bit in the ‘0’ state. Code
protection bits are only set to ‘1’ by a full
chip erase or block erase function. The full
chip erase and block erase functions can
only be initiated via ICSP or an external
programmer.
CP3
Bit 3
—
—
—
(1)
(1)
(1)
EBTR2
WRT2
Bit 2
CP2
—
—
—
EBTR1
WRT1
Bit 1
CP1
DS39612B-page 271
—
—
—
EBTR0
WRT0
Bit 0
CP0
—
—
—