PIC18F6680-I/PT Microchip Technology Inc., PIC18F6680-I/PT Datasheet - Page 87

• Manufacturer Part Number: PIC18F6680-I/PT
• Description: 64 PIN, 64 KB FLASH, 3328 RAM, 52 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F6680-I/PT

• A/d Inputs: 12-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1024 Bytes
• Input Output: 53
• Interface: CAN/I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 64-pin TQFP
• Programmable Memory: 64K Bytes
• Ram Size: 3.3K Bytes
• Speed: 40 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

8.0
8.1
An 8 x 8 hardware multiplier is included in the ALU of the
PIC18F6525/6621/8525/8621 devices. By making the
multiply a hardware operation, it completes in a single
instruction cycle. This is an unsigned multiply that gives
a 16-bit result. The result is stored in the 16-bit product
register pair (PRODH:PRODL). The multiplier does not
affect any flags in the ALUSTA register.
Making the 8 x 8 multiplier execute in a single cycle
gives the following advantages:
• Higher computational throughput
• Reduces code size requirements for multiply
The performance increase allows the device to be used
in applications previously reserved for Digital Signal
Processors.
Table 8-1 shows a performance comparison between
Enhanced devices using the single-cycle hardware
multiply and performing the same function without the
hardware multiply.
TABLE 8-1:
 2005 Microchip Technology Inc.
16 x 16 unsigned
algorithms
8 x 8 unsigned
16 x 16 signed
8 x 8 signed
Routine
8 x 8 HARDWARE MULTIPLIER
Introduction
PERFORMANCE COMPARISON
Without hardware multiply
Without hardware multiply
Without hardware multiply
Without hardware multiply
Hardware multiply
Hardware multiply
Hardware multiply
Hardware multiply
Multiply Method
PIC18F6525/6621/8525/8621
Program
Memory
(Words)
13
33
21
24
52
36
1
6
8.2
Example 8-1 shows the sequence to do an 8 x 8
unsigned multiply. Only one instruction is required
when one argument of the multiply is already loaded in
the WREG register.
Example 8-2 shows the sequence to do an 8 x 8 signed
multiply. To account for the signed bits of the
arguments, each argument’s Most Significant bit (MSb)
is tested and the appropriate subtractions are done.
EXAMPLE 8-1:
EXAMPLE 8-2:
MOVF
MULWF ARG2
MOVF
MULWF ARG2
BTFSC ARG2, SB
SUBWF PRODH, F
MOVF
BTFSC ARG1, SB
SUBWF PRODH, F
Cycles
(Max)
242
254
69
91
24
36
1
6
Operation
ARG1, W
ARG1, W
ARG2, W
@ 40 MHz
24.2 µs
25.4 µs
100 ns
600 ns
6.9 µs
9.1 µs
2.4 µs
3.6 µs
8 x 8 UNSIGNED
MULTIPLY ROUTINE
8 x 8 SIGNED MULTIPLY
ROUTINE
;
; ARG1 * ARG2 ->
;
;
; ARG1 * ARG2 ->
; PRODH:PRODL
; Test Sign Bit
; PRODH = PRODH
;
;
; Test Sign Bit
; PRODH = PRODH
;
PRODH:PRODL
@ 10 MHz
102.6 µs
27.6 µs
36.4 µs
96.8 µs
14.4 µs
Time
400 ns
2.4 µs
9.6 µs
DS39612B-page 85
- ARG1
- ARG2
@ 4 MHz
242 µs
254 µs
69 µs
91 µs
24 µs
36 µs
1 µs
6 µs