PIC18F6680-I/PT Microchip Technology Inc., PIC18F6680-I/PT Datasheet - Page 31

• Manufacturer Part Number: PIC18F6680-I/PT
• Description: 64 PIN, 64 KB FLASH, 3328 RAM, 52 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F6680-I/PT

• A/d Inputs: 12-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1024 Bytes
• Input Output: 53
• Interface: CAN/I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 64-pin TQFP
• Programmable Memory: 64K Bytes
• Ram Size: 3.3K Bytes
• Speed: 40 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

3.0
The PIC18F6525/6621/8525/8621 devices differentiate
between various kinds of Reset:
a)
b)
c)
d)
e)
f)
g)
h)
Most registers are unaffected by a Reset. Their status
is unknown on POR and unchanged by all other
Resets. The other registers are forced to a “Reset
state” on Power-on Reset, MCLR, WDT Reset, Brown-
out Reset, MCLR Reset during Sleep and by the
RESET instruction.
FIGURE 3-1:
 2005 Microchip Technology Inc.
MCLR
OSC1
V
Note 1: This is a separate oscillator from the RC oscillator of the CLKI pin.
Power-on Reset (POR)
MCLR Reset during normal operation
MCLR Reset during Sleep
Watchdog Timer (WDT) Reset (during normal
operation)
Programmable Brown-out Reset (BOR)
RESET Instruction
Stack Full Reset
Stack Underflow Reset
DD
RESET
2: See Table 3-1 for time-out situations.
RC OSC
OST/PWRT
On-chip
Pointer
Stack
Brown-out
V
(1)
Module
DD
Detect
WDT
Reset
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
RESET Instruction
Stack Full/Underflow Reset
Rise
OST
PWRT
External Reset
10-bit Ripple Counter
10-bit Ripple Counter
Time-out
Reset
WDT
Power-on Reset
Sleep
BOR
PIC18F6525/6621/8525/8621
Most registers are not affected by a WDT wake-up
since this is viewed as the resumption of normal oper-
ation. Status bits from the RCON register, RI, TO, PD,
POR and BOR, are set or cleared differently in different
Reset situations as indicated in Table 3-2. These bits
are used in software to determine the nature of the
Reset. See Table 3-3 for a full description of the Reset
states of all registers.
A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 3-1.
The Enhanced MCU devices have a MCLR noise filter
in the MCLR Reset path. The filter will detect and
ignore small pulses. The MCLR pin is not driven low by
any internal Resets, including the WDT.
S
R
Enable PWRT
Enable OST
DS39612B-page 29
Q
Chip_Reset
(2)