PIC16F1827-I/ML Microchip Technology Inc., PIC16F1827-I/ML Datasheet - Page 197
![no-image](/images/manufacturer_photos/0/4/440/microchip_technology_inc__sml.jpg)
PIC16F1827-I/ML
Manufacturer Part Number
PIC16F1827-I/ML
Description
28 QFN 6x6mm TUBE, 7 KB Flash, 384 bytes RAM, 32 MHz Int. Osc, 16 I/0, Enhanced
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC16F1826-ISO.pdf
(406 pages)
Specifications of PIC16F1827-I/ML
A/d Inputs
12-Channel, 10-Bit
Comparators
2
Cpu Speed
8 MIPS
Eeprom Memory
256 Bytes
Input Output
16
Interface
CAN/I2C/SPI/UART/USART
Memory Type
Flash
Number Of Bits
8
Package Type
18-pin QFN
Programmable Memory
7K Bytes
Ram Size
384 Bytes
Speed
32 MHz
Timers
4-8-bit, 1-16-bit
Voltage, Range
1.8-5.5 V
Standby Current (pic16lf182x)
30 nA @ 1.8 V, Typical
Lead Free Status / Rohs Status
RoHS Compliant part
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23.5
The signal provided from any selected input source for
the carrier high and carrier low signals can be inverted.
Inverting the signal for the carrier high source is
enabled by setting the MDCHPOL bit of the MDCARH
register. Inverting the signal for the carrier low source is
enabled by setting the MDCLPOL bit of the MDCARL
register.
23.6
Some peripherals assert control over their correspond-
ing output pin when they are enabled. For example,
when the CCP1 module is enabled, the output of CCP1
is connected to the CCP1 pin.
This default connection to a pin can be disabled by set-
ting the MDCHODIS bit in the MDCARH register for the
carrier high source and the MDCLODIS bit in the
MDCARL register for the carrier low source.
23.7
The MDBIT of the MDCON register can be selected as
the source for the modulator signal. This gives the user
the ability to program the value used for modulation.
23.8
The modulator source default connection to a pin can
be disabled by setting the MDMSODIS bit in the
MDSRC register.
23.9
The modulated output signal provided on the MDOUT
pin can also be inverted. Inverting the modulated out-
put signal is enabled by setting the MDOPOL bit of the
MDCON register.
23.10 Slew Rate Control
The slew rate limitation on the output port pin can be
disabled. The slew rate limitation can be removed by
clearing the MDSLR bit in the MDCON register.
2011 Microchip Technology Inc.
Carrier Source Polarity Select
Carrier Source Pin Disable
Programmable Modulator Data
Modulator Source Pin Disable
Modulated Output Polarity
23.11 Operation in Sleep Mode
The DSM module is not affected by Sleep mode. The
DSM can still operate during Sleep, if the Carrier and
Modulator input sources are also still operable during
Sleep.
23.12 Effects of a Reset
Upon any device Reset, the data signal modulator
module is disabled. The user's firmware is responsible
for initializing the module before enabling the output.
The registers are reset to their default values.
PIC16(L)F1826/27
DS41391D-page 197
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