PIC16F1827-I/MV Microchip Technology Inc., PIC16F1827-I/MV Datasheet - Page 160
PIC16F1827-I/MV
Manufacturer Part Number
PIC16F1827-I/MV
Description
28 UQFN 4x4x0.5mm TUBE, 7 KB Flash, 384 bytes RAM, 32 MHz Int. Osc, 16 I/0, Enha
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC16F1826-ISO.pdf
(406 pages)
Specifications of PIC16F1827-I/MV
A/d Inputs
12-Channel, 10-Bit
Comparators
2
Cpu Speed
8 MIPS
Eeprom Memory
256 Bytes
Input Output
16
Interface
CAN/I2C/SPI/UART/USART
Memory Type
Flash
Number Of Bits
8
Package Type
18-pin UQFN
Programmable Memory
7K Bytes
Ram Size
384 Bytes
Speed
32 MHz
Timers
4-8-bit, 1-16-bit
Voltage, Range
1.8-5.5 V
Standby Current (pic16lf182x)
30 nA @ 1.8 V, Typical
Lead Free Status / Rohs Status
RoHS Compliant part
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PIC16(L)F1826/27
REGISTER 18-2:
DS41391D-page 160
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W-0/0
SRSPE
SRSPE: SR Latch Peripheral Set Enable bit
1 = SR Latch is set when the SRI pin is high.
0 = SRI pin has no effect on the set input of the SR Latch
SRSCKE: SR Latch Set Clock Enable bit
1 = Set input of SR Latch is pulsed with SRCLK
0 = SRCLK has no effect on the set input of the SR Latch
SRSC2E: SR Latch C2 Set Enable bit
1 = SR Latch is set when the C2 Comparator output is high
0 = C2 Comparator output has no effect on the set input of the SR Latch
SRSC1E: SR Latch C1 Set Enable bit
1 = SR Latch is set when the C1 Comparator output is high
0 = C1 Comparator output has no effect on the set input of the SR Latch
SRRPE: SR Latch Peripheral Reset Enable bit
1 = SR Latch is reset when the SRI pin is high.
0 = SRI pin has no effect on the reset input of the SR Latch
SRRCKE: SR Latch Reset Clock Enable bit
1 = Reset input of SR Latch is pulsed with SRCLK
0 = SRCLK has no effect on the reset input of the SR Latch
SRRC2E: SR Latch C2 Reset Enable bit
1 = SR Latch is reset when the C2 Comparator output is high
0 = C2 Comparator output has no effect on the reset input of the SR Latch
SRRC1E: SR Latch C1 Reset Enable bit
1 = SR Latch is reset when the C1 Comparator output is high
0 = C1 Comparator output has no effect on the reset input of the SR Latch
SRSCKE
R/W-0/0
SRCON1: SR LATCH CONTROL 1 REGISTER
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
SRSC2E
R/W-0/0
SRSC1E
R/W-0/0
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
R/W-0/0
SRRPE
SRRCKE
R/W-0/0
2011 Microchip Technology Inc.
SRRC2E
R/W-0/0
SRRC1E
R/W-0/0
bit 0
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