PIC16F1827-I/MV Microchip Technology Inc., PIC16F1827-I/MV Datasheet - Page 44
PIC16F1827-I/MV
Manufacturer Part Number
PIC16F1827-I/MV
Description
28 UQFN 4x4x0.5mm TUBE, 7 KB Flash, 384 bytes RAM, 32 MHz Int. Osc, 16 I/0, Enha
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC16F1826-ISO.pdf
(406 pages)
Specifications of PIC16F1827-I/MV
A/d Inputs
12-Channel, 10-Bit
Comparators
2
Cpu Speed
8 MIPS
Eeprom Memory
256 Bytes
Input Output
16
Interface
CAN/I2C/SPI/UART/USART
Memory Type
Flash
Number Of Bits
8
Package Type
18-pin UQFN
Programmable Memory
7K Bytes
Ram Size
384 Bytes
Speed
32 MHz
Timers
4-8-bit, 1-16-bit
Voltage, Range
1.8-5.5 V
Standby Current (pic16lf182x)
30 nA @ 1.8 V, Typical
Lead Free Status / Rohs Status
RoHS Compliant part
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PIC16(L)F1826/27
REGISTER 4-1:
DS41391D-page 44
bit 7
Legend:
R = Readable bit
‘0’ = Bit is cleared
bit 13
bit 12
bit 11
bit 10-9
bit 8
bit 7
bit 6
bit 5
bit 4-3
R/P-1
CP
FCMEN: Fail-Safe Clock Monitor Enable bit
1 = Fail-Safe Clock Monitor is enabled
0 = Fail-Safe Clock Monitor is disabled
IESO: Internal External Switchover bit
1 = Internal/External Switchover mode is enabled
0 = Internal/External Switchover mode is disabled
CLKOUTEN: Clock Out Enable bit
If FOSC configuration bits are set to LP, XT, HS modes:
All other FOSC modes:
BOREN<1:0>: Brown-out Reset Enable bits
11 = BOR enabled
10 = BOR enabled during operation and disabled in Sleep
01 = BOR controlled by SBOREN bit of the BORCON register
00 = BOR disabled
CPD: Data Code Protection bit
1 = Data memory code protection is disabled
0 = Data memory code protection is enabled
CP: Code Protection bit
1 = Program memory code protection is disabled
0 = Program memory code protection is enabled
MCLRE: MCLR/V
If LVP bit = 1:
If LVP bit = 0:
PWRTE: Power-up Timer Enable bit
1 = PWRT disabled
0 = PWRT enabled
WDTE<1:0>: Watchdog Timer Enable bit
11 = WDT enabled
10 = WDT enabled while running and disabled in Sleep
01 = WDT controlled by the SWDTEN bit in the WDTCON register
00 = WDT disabled
MCLRE
R/P-1
This bit is ignored.
1 = MCLR/V
0 = MCLR/V
This bit is ignored, CLKOUT function is disabled. Oscillator function on the CLKOUT pin.
1 = CLKOUT function is disabled. I/O function on the CLKOUT pin.
0 = CLKOUT function is enabled on the CLKOUT pin
CONFIGURATION WORD 1
WPUE3 bit.
bit 13
P = Programmable bit
‘1’ = Bit is set
PP
PP
PWRTE
FCMEN
PP
R/P-1
R/P-1
pin function is MCLR; Weak pull-up enabled.
pin function is digital input; MCLR internally disabled; Weak pull-up under control of
Pin Function Select bit
(2)
R/P-1
R/P-1
IESO
WDTE<1:0>
U = Unimplemented bit, read as ‘1’
-n = Value when blank or after Bulk Erase
CLKOUTEN
R/P-1
R/P-1
R/P-1
R/P-1
BOREN<1:0>
2011 Microchip Technology Inc.
FOSC<2:0>
R/P-1
R/P-1
R/P-1/1
R/P-1
CPD
bit 8
bit 0
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