PIC16F1827-I/MV Microchip Technology Inc., PIC16F1827-I/MV Datasheet - Page 331
PIC16F1827-I/MV
Manufacturer Part Number
PIC16F1827-I/MV
Description
28 UQFN 4x4x0.5mm TUBE, 7 KB Flash, 384 bytes RAM, 32 MHz Int. Osc, 16 I/0, Enha
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC16F1826-ISO.pdf
(406 pages)
Specifications of PIC16F1827-I/MV
A/d Inputs
12-Channel, 10-Bit
Comparators
2
Cpu Speed
8 MIPS
Eeprom Memory
256 Bytes
Input Output
16
Interface
CAN/I2C/SPI/UART/USART
Memory Type
Flash
Number Of Bits
8
Package Type
18-pin UQFN
Programmable Memory
7K Bytes
Ram Size
384 Bytes
Speed
32 MHz
Timers
4-8-bit, 1-16-bit
Voltage, Range
1.8-5.5 V
Standby Current (pic16lf182x)
30 nA @ 1.8 V, Typical
Lead Free Status / Rohs Status
RoHS Compliant part
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CALL
Syntax:
Operands:
Operation:
Status Affected:
Description:
CALLW
Syntax:
Operands:
Operation:
Status Affected:
Description:
CLRF
Syntax:
Operands:
Operation:
Status Affected:
Description:
CLRW
Syntax:
Operands:
Operation:
Status Affected:
Description:
2011 Microchip Technology Inc.
Call Subroutine
[ label ] CALL k
0 k 2047
(PC)+ 1 TOS,
k PC<10:0>,
(PCLATH<6:3>) PC<14:11>
None
Call Subroutine. First, return address
(PC + 1) is pushed onto the stack.
The eleven-bit immediate address is
loaded into PC bits <10:0>. The upper
bits of the PC are loaded from
PCLATH. CALL is a two-cycle instruc-
tion.
Clear W
[ label ] CLRW
None
00h (W)
1 Z
Z
W register is cleared. Zero bit (Z) is
set.
[ label ] CALLW
(PC) +1 TOS,
(W) PC<7:0>,
(PCLATH<6:0>) PC<14:8>
Subroutine call with W. First, the
return address (PC + 1) is pushed
onto the return stack. Then, the con-
tents of W is loaded into PC<7:0>,
and the contents of PCLATH into
PC<14:8>. CALLW is a two-cycle
instruction.
Subroutine Call With W
None
None
Clear f
[ label ] CLRF
0 f 127
00h (f)
1 Z
Z
The contents of register ‘f’ are cleared
and the Z bit is set.
f
CLRWDT
Syntax:
Operands:
Operation:
Status Affected:
Description:
COMF
Syntax:
Operands:
Operation:
Status Affected:
Description:
DECF
Syntax:
Operands:
Operation:
Status Affected:
Description:
PIC16(L)F1826/27
Complement f
[ label ] COMF
0 f 127
d [0,1]
(f) (destination)
Z
The contents of register ‘f’ are com-
plemented. If ‘d’ is ‘0’, the result is
stored in W. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
Decrement f
[ label ] DECF f,d
0 f 127
d [0,1]
(f) - 1 (destination)
Z
result is stored in the W
register. If ‘d’ is ‘1’, the result is stored
back in register ‘f’.
Clear Watchdog Timer
[ label ] CLRWDT
None
00h WDT
0 WDT prescaler,
1 TO
1 PD
TO, PD
CLRWDT instruction resets the Watch-
dog Timer. It also resets the prescaler
of the WDT.
Status bits TO and PD are set.
Decrement register ‘f’. If ‘d’ is ‘0’, the
f,d
DS41391D-page 331
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